1/* 2 * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m33"; 18 reg = <0>; 19 cpu-power-states = <&idle &suspend_to_ram>; 20 }; 21 22 power-states { 23 idle: idle { 24 compatible = "zephyr,power-state"; 25 power-state-name = "suspend-to-idle"; 26 min-residency-us = <1000000>; 27 }; 28 29 suspend_to_ram: suspend_to_ram { 30 compatible = "zephyr,power-state"; 31 power-state-name = "suspend-to-ram"; 32 min-residency-us = <2000000>; 33 }; 34 }; 35 }; 36 37 sram0: memory@20000000 { 38 compatible = "mmio-sram"; 39 reg = <0x20000000 DT_SIZE_K(244)>; 40 }; 41 42 sram_bootstrap: memory@2003D000 { 43 compatible = "zephyr,memory-region", "mmio-sram"; 44 zephyr,memory-region = "BOOTSTRAP_RAM"; 45 reg = <0x2003D000 DT_SIZE_K(12)>; 46 }; 47 48 soc { 49 pinctrl: pinctrl@40400000 { 50 compatible = "infineon,cat1-pinctrl"; 51 reg = <0x40400000 0x20000>; 52 }; 53 54 hsiom: hsiom@40400000 { 55 compatible = "infineon,cat1-hsiom"; 56 reg = <0x40400000 0x4000>; 57 interrupts = <7 4>, <6 4>; 58 status = "disabled"; 59 }; 60 61 gpio_prt0: gpio@40410000 { 62 compatible = "infineon,cat1-gpio"; 63 reg = <0x40410000 0x80>; 64 interrupts = <0 4>; 65 gpio-controller; 66 ngpios = <6>; 67 status = "disabled"; 68 #gpio-cells = <2>; 69 }; 70 gpio_prt1: gpio@40410080 { 71 compatible = "infineon,cat1-gpio"; 72 reg = <0x40410080 0x80>; 73 interrupts = <1 4>; 74 gpio-controller; 75 ngpios = <7>; 76 status = "disabled"; 77 #gpio-cells = <2>; 78 }; 79 gpio_prt2: gpio@40410100 { 80 compatible = "infineon,cat1-gpio"; 81 reg = <0x40410100 0x80>; 82 interrupts = <2 4>; 83 gpio-controller; 84 ngpios = <6>; 85 status = "disabled"; 86 #gpio-cells = <2>; 87 }; 88 gpio_prt3: gpio@40410180 { 89 compatible = "infineon,cat1-gpio"; 90 reg = <0x40410180 0x80>; 91 interrupts = <3 4>; 92 gpio-controller; 93 ngpios = <8>; 94 status = "disabled"; 95 #gpio-cells = <2>; 96 }; 97 gpio_prt4: gpio@40410200 { 98 compatible = "infineon,cat1-gpio"; 99 reg = <0x40410200 0x80>; 100 interrupts = <4 4>; 101 gpio-controller; 102 ngpios = <2>; 103 status = "disabled"; 104 #gpio-cells = <2>; 105 }; 106 gpio_prt5: gpio@40410280 { 107 compatible = "infineon,cat1-gpio"; 108 reg = <0x40410280 0x80>; 109 interrupts = <5 4>; 110 gpio-controller; 111 ngpios = <3>; 112 status = "disabled"; 113 #gpio-cells = <2>; 114 }; 115 116 adc0: adc@40520000 { 117 compatible = "infineon,cat1-adc"; 118 reg = <0x40520000 0x10000>; 119 interrupts = <67 6>; 120 status = "disabled"; 121 #io-channel-cells = <1>; 122 }; 123 124 ipc0: ipc@401d0000 { 125 compatible = "infineon,cat1-ipc"; 126 reg = <0x401d0000 0x10000>; 127 status = "disabled"; 128 #ipc-config-cells = <3>; 129 }; 130 131 scb0: scb@40590000 { 132 compatible = "infineon,cat1-scb"; 133 reg = <0x40590000 0xfd0>; 134 interrupts = <8 4>; 135 status = "disabled"; 136 }; 137 scb1: scb@405a0000 { 138 compatible = "infineon,cat1-scb"; 139 reg = <0x405a0000 0xfd0>; 140 interrupts = <17 4>; 141 status = "disabled"; 142 }; 143 scb2: scb@405b0000 { 144 compatible = "infineon,cat1-scb"; 145 reg = <0x405b0000 0xfd0>; 146 interrupts = <18 4>; 147 status = "disabled"; 148 }; 149 150 watchdog0: watchdog@4020c000 { 151 compatible = "infineon,cat1-watchdog"; 152 reg = <0x4020c000 0x10>; 153 interrupts = <15 4>; 154 status = "disabled"; 155 }; 156 157 mcwdt0: mcwdt@4020d000 { 158 compatible = "infineon,cat1-lp-timer"; 159 reg = <0x4020d000 0x40>; 160 interrupts = <9 4>; 161 status = "disabled"; 162 }; 163 164 rtc0: rtc@40220000 { 165 compatible = "infineon,cat1-rtc"; 166 reg = <0x40220000 0x10000>; 167 interrupts = <10 6>; 168 alarms-count = <2>; 169 status = "disabled"; 170 }; 171 172 counter0_0: counter@404a0000 { 173 compatible = "infineon,cat1-counter"; 174 reg = <0x404a0000 0x80>; 175 interrupts = <42 4>; 176 resolution = <32>; 177 status = "disabled"; 178 }; 179 counter0_1: counter@404a0080 { 180 compatible = "infineon,cat1-counter"; 181 reg = <0x404a0080 0x80>; 182 interrupts = <43 4>; 183 resolution = <32>; 184 status = "disabled"; 185 }; 186 counter1_0: counter@404a8000 { 187 compatible = "infineon,cat1-counter"; 188 reg = <0x404a8000 0x80>; 189 interrupts = <44 4>; 190 resolution = <16>; 191 status = "disabled"; 192 }; 193 counter1_1: counter@404a8080 { 194 compatible = "infineon,cat1-counter"; 195 reg = <0x404a8080 0x80>; 196 interrupts = <45 4>; 197 resolution = <16>; 198 status = "disabled"; 199 }; 200 counter1_2: counter@404a8100 { 201 compatible = "infineon,cat1-counter"; 202 reg = <0x404a8100 0x80>; 203 interrupts = <46 4>; 204 resolution = <16>; 205 status = "disabled"; 206 }; 207 counter1_3: counter@404a8180 { 208 compatible = "infineon,cat1-counter"; 209 reg = <0x404a8180 0x80>; 210 interrupts = <47 4>; 211 resolution = <16>; 212 status = "disabled"; 213 }; 214 counter1_4: counter@404a8200 { 215 compatible = "infineon,cat1-counter"; 216 reg = <0x404a8200 0x80>; 217 interrupts = <48 4>; 218 resolution = <16>; 219 status = "disabled"; 220 }; 221 counter1_5: counter@404a8280 { 222 compatible = "infineon,cat1-counter"; 223 reg = <0x404a8280 0x80>; 224 interrupts = <49 4>; 225 resolution = <16>; 226 status = "disabled"; 227 }; 228 counter1_6: counter@404a8300 { 229 compatible = "infineon,cat1-counter"; 230 reg = <0x404a8300 0x80>; 231 interrupts = <50 4>; 232 resolution = <16>; 233 status = "disabled"; 234 }; 235 236 pwm0_0: pwm@404a0000 { 237 compatible = "infineon,cat1-pwm"; 238 reg = <0x404a0000 0x80>; 239 interrupts = <42 4>; 240 resolution = <32>; 241 status = "disabled"; 242 #pwm-cells = <3>; 243 }; 244 pwm0_1: pwm@404a0080 { 245 compatible = "infineon,cat1-pwm"; 246 reg = <0x404a0080 0x80>; 247 interrupts = <43 4>; 248 resolution = <32>; 249 status = "disabled"; 250 #pwm-cells = <3>; 251 }; 252 pwm1_0: pwm@404a8000 { 253 compatible = "infineon,cat1-pwm"; 254 reg = <0x404a8000 0x80>; 255 interrupts = <44 4>; 256 resolution = <16>; 257 status = "disabled"; 258 #pwm-cells = <3>; 259 }; 260 pwm1_1: pwm@404a8080 { 261 compatible = "infineon,cat1-pwm"; 262 reg = <0x404a8080 0x80>; 263 interrupts = <45 4>; 264 resolution = <16>; 265 status = "disabled"; 266 #pwm-cells = <3>; 267 }; 268 pwm1_2: pwm@404a8100 { 269 compatible = "infineon,cat1-pwm"; 270 reg = <0x404a8100 0x80>; 271 interrupts = <46 4>; 272 resolution = <16>; 273 status = "disabled"; 274 #pwm-cells = <3>; 275 }; 276 pwm1_3: pwm@404a8180 { 277 compatible = "infineon,cat1-pwm"; 278 reg = <0x404a8180 0x80>; 279 interrupts = <47 4>; 280 resolution = <16>; 281 status = "disabled"; 282 #pwm-cells = <3>; 283 }; 284 pwm1_4: pwm@404a8200 { 285 compatible = "infineon,cat1-pwm"; 286 reg = <0x404a8200 0x80>; 287 interrupts = <48 4>; 288 resolution = <16>; 289 status = "disabled"; 290 #pwm-cells = <3>; 291 }; 292 pwm1_5: pwm@404a8280 { 293 compatible = "infineon,cat1-pwm"; 294 reg = <0x404a8280 0x80>; 295 interrupts = <49 4>; 296 resolution = <16>; 297 status = "disabled"; 298 #pwm-cells = <3>; 299 }; 300 pwm1_6: pwm@404a8300 { 301 compatible = "infineon,cat1-pwm"; 302 reg = <0x404a8300 0x80>; 303 interrupts = <50 4>; 304 resolution = <16>; 305 status = "disabled"; 306 #pwm-cells = <3>; 307 }; 308 309 dma0: dw@40180000 { 310 #dma-cells = <1>; 311 compatible = "infineon,cat1-dma"; 312 reg = <0x40180000 0x10000>; 313 dma-channels = <16>; 314 interrupts = <19 4>, /* CH0 */ 315 <20 4>, /* CH1 */ 316 <21 4>, /* CH2 */ 317 <22 4>, /* CH3 */ 318 <23 4>, /* CH4 */ 319 <24 4>, /* CH5 */ 320 <25 4>, /* CH6 */ 321 <26 4>, /* CH7 */ 322 <27 4>, /* CH8 */ 323 <28 4>, /* CH9 */ 324 <29 4>, /* CH10 */ 325 <30 4>, /* CH11 */ 326 <31 4>, /* CH12 */ 327 <32 4>, /* CH13 */ 328 <33 4>, /* CH14 */ 329 <34 4>; /* CH15 */ 330 status = "disabled"; 331 }; 332 bluetooth: btss@42000000 { 333 compatible = "infineon,cyw208xx-hci"; 334 reg = <0x42000000 0x6186A0>; 335 interrupts = <16 4>; 336 status = "disabled"; 337 }; 338 339 }; 340}; 341
