1/*
2 * Copyright 2022-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10#include <dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
12#include <dt-bindings/adc/nxp,gau-adc.h>
13#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
14#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &trng;
19		zephyr,nbu = &nbu;
20		zephyr,bt-hci = &hci;
21		zephyr,hdlc-rcp-if = &hdlc_rcp_if;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			compatible = "arm,cortex-m33f";
30			reg = <0>;
31			#address-cells = <1>;
32			#size-cells = <1>;
33			cpu-power-states = <&idle &suspend>;
34
35			mpu: mpu@e000ed90 {
36				compatible = "arm,armv8m-mpu";
37				reg = <0xe000ed90 0x40>;
38			};
39		};
40
41		power-states {
42			/* Idle mode maps to Power Mode 1 */
43			idle: idle {
44				compatible = "zephyr,power-state";
45				power-state-name = "runtime-idle";
46				min-residency-us = <0>;
47				exit-latency-us = <0>;
48			};
49			/* Suspend mode maps to Power Mode 2 */
50			suspend: suspend {
51				compatible = "nxp,pdcfg-power", "zephyr,power-state";
52				power-state-name = "suspend-to-idle";
53				min-residency-us = <500>;
54				exit-latency-us = <120>;
55				deep-sleep-config = <0x180000>,
56							<0x0>,
57							<0x4>,
58							<0x100>,
59							<0x0>;
60			};
61		};
62	};
63
64	smu1: sram@41380000 {
65		ranges = <0x0 0x41380000 DT_SIZE_K(510)>;
66	};
67
68	smu2: sram@443C0000 {
69		ranges = <0x0 0x443C0000 DT_SIZE_K(140)>;
70	};
71
72};
73
74&sram {
75	#address-cells = <1>;
76	#size-cells = <1>;
77
78	sram_data: memory@40000 {
79		compatible = "mmio-sram";
80		reg = <0x40000 DT_SIZE_K(960)>;
81	};
82
83	sram_code: memory@0 {
84		compatible = "mmio-sram";
85		reg = <0x00000000 DT_SIZE_K(256)>;
86	};
87};
88
89&smu1 {
90	#address-cells = <1>;
91	#size-cells = <1>;
92
93	smu1_data: memory@0 {
94		compatible = "zephyr,memory-region","mmio-sram";
95		reg = <0x0 DT_SIZE_K(510)>;
96		zephyr,memory-region = "SMU1";
97		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
98	};
99};
100
101&smu2 {
102	#address-cells = <1>;
103	#size-cells = <1>;
104
105	smu2_data: memory@0 {
106		compatible = "zephyr,memory-region","mmio-sram";
107		reg = <0x0 DT_SIZE_K(140)>;
108		zephyr,memory-region = "SMU2";
109		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
110	};
111};
112
113&peripheral {
114	#address-cells = <1>;
115	#size-cells = <1>;
116
117	flexspi: spi@134000 {
118		reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
119	};
120
121	clkctl0: clkctl@1000 {
122		/* FIXME This chip does NOT have a syscon */
123		compatible = "nxp,lpc-syscon";
124		reg = <0x1000 0x1000>;
125		#clock-cells = <1>;
126	};
127
128	pinctrl: mci_iomux@4000 {
129		compatible = "nxp,mci-io-mux";
130		reg = <0x4000 0x1000>;
131		status = "okay";
132	};
133
134	clkctl1: clkctl@21000 {
135		/* FIXME This chip does NOT have a syscon */
136		compatible = "nxp,lpc-syscon";
137		reg = <0x21000 0x1000>;
138		#clock-cells = <1>;
139	};
140
141	rstctl0: reset@0 {
142		compatible = "nxp,rstctl";
143		reg = <0x0 0x80>;
144		#reset-cells = <1>;
145	};
146
147	rstctl1: reset@20000 {
148		compatible = "nxp,rstctl";
149		reg = <0x20000 0x80>;
150		#reset-cells = <1>;
151	};
152
153	pmu: pmu@31000 {
154		reg = <0x31000 0x130>;
155		compatible = "nxp,rw-pmu";
156		pin0: pin0 {
157			compatible = "nxp,aon-wakeup-pin";
158			interrupts = <100 0>;
159			status = "disabled";
160		};
161		pin1: pin1 {
162			compatible = "nxp,aon-wakeup-pin";
163			interrupts = <101 0>;
164			status = "disabled";
165		};
166	};
167
168	trng: random@14000 {
169		compatible = "nxp,kinetis-trng";
170		reg = <0x14000 0x1000>;
171		status = "okay";
172		interrupts = <123 0>;
173	};
174
175	wwdt: watchdog@e000 {
176		compatible = "nxp,lpc-wwdt";
177		reg = <0xe000 0x1000>;
178		interrupts = <0 0>;
179		status = "disabled";
180		clk-divider = <1>;
181	};
182
183	hsgpio: hsgpio@100000 {
184		compatible = "nxp,lpc-gpio";
185		reg = <0x100000 0x4000>;
186		#address-cells = <1>;
187		#size-cells = <0>;
188
189		hsgpio0: gpio@0 {
190			compatible = "nxp,lpc-gpio-port";
191			gpio-controller;
192			#gpio-cells = <2>;
193			reg = <0>;
194			int-source = "pint";
195		};
196
197		hsgpio1: gpio@1 {
198			compatible = "nxp,lpc-gpio-port";
199			gpio-controller;
200			#gpio-cells = <2>;
201			reg = <1>;
202			int-source = "pint";
203		};
204	};
205
206	usb_otg: usbotg@145000 {
207		compatible = "nxp,ehci";
208		reg = <0x145000 0x200>;
209		interrupts = <50 1>;
210		interrupt-names = "usb_otg";
211		num-bidir-endpoints = <8>;
212		status = "disabled";
213	};
214
215	flexcomm0: flexcomm@106000 {
216		compatible = "nxp,lpc-flexcomm";
217		reg = <0x106000 0x1000>;
218		interrupts = <14 0>;
219		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
220		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
221		dmas = <&dma0 0>, <&dma0 1>;
222		dma-names = "rx", "tx";
223		status = "disabled";
224	};
225
226	flexcomm1: flexcomm@107000 {
227		compatible = "nxp,lpc-flexcomm";
228		reg = <0x107000 0x1000>;
229		interrupts = <15 0>;
230		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
231		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
232		dmas = <&dma0 2>, <&dma0 3>;
233		dma-names = "rx", "tx";
234		status = "disabled";
235	};
236
237	flexcomm2: flexcomm@108000 {
238		compatible = "nxp,lpc-flexcomm";
239		reg = <0x108000 0x1000>;
240		interrupts = <16 0>;
241		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
242		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
243		dmas = <&dma0 4>, <&dma0 5>;
244		dma-names = "rx", "tx";
245		status = "disabled";
246	};
247
248	flexcomm3: flexcomm@109000 {
249		compatible = "nxp,lpc-flexcomm";
250		reg = <0x109000 0x1000>;
251		interrupts = <17 0>;
252		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
253		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
254		dmas = <&dma0 6>, <&dma0 7>;
255		dma-names = "rx", "tx";
256		status = "disabled";
257	};
258
259	flexcomm14: flexcom@126000 {
260		compatible = "nxp,lpc-flexcomm";
261		reg = <0x126000 0x2000>;
262		interrupts = <20 0>;
263		clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>;
264		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
265		dmas = <&dma0 26>, <&dma0 27>;
266		dma-names = "rx", "tx";
267		status = "disabled";
268	};
269
270	aon_soc_ctrl: aon_soc_ctrl@5000800 {
271		compatible = "nxp,rw-soc-ctrl";
272		reg = <0x5000800 0x1000>;
273		status = "okay";
274	};
275
276	soc_ctrl: soc_ctrl@5001000 {
277		compatible = "nxp,rw-soc-ctrl";
278		reg = <0x5001000 0x1000>;
279		status = "okay";
280	};
281
282	pint: pint@25000 {
283		compatible = "nxp,pint";
284		reg = <0x25000 0x1000>;
285		interrupt-controller;
286		#interrupt-cells = <1>;
287		#address-cells = <0>;
288		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
289			<35 2>, <36 2>, <37 2>, <38 2>;
290		num-lines = <8>;
291		num-inputs = <64>;
292	};
293
294	imu: nxp_wifi {
295		compatible = "nxp,wifi";
296		/* first index is the imu interrupt, the second is the wakeup done interrupt */
297		interrupts = <72 2>, <64 2>;
298	};
299
300	dma0: dma-controller@104000 {
301		compatible = "nxp,lpc-dma";
302		reg = <0x104000 0x1000>;
303		interrupts = <1 0>;
304		status = "disabled";
305		#dma-cells = <1>;
306		dma-channels = <33>;
307	};
308
309	lcdic: lcdic@128000 {
310		compatible = "nxp,lcdic";
311		reg = <0x128000 0x52>;
312		interrupts = <61 0>;
313		status = "disabled";
314		#address-cells = <1>;
315		#size-cells = <0>;
316		clocks = <&clkctl1 MCUX_LCDIC_CLK>;
317		dmas = <&dma0 0>;
318	};
319
320	ctimer0: ctimer@28000 {
321		compatible = "nxp,lpc-ctimer";
322		reg = <0x28000 0x1000>;
323		interrupts = <10 0>;
324		status = "disabled";
325		clk-source = <1>;
326		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
327		mode = <0>;
328		input = <0>;
329		prescale = <0>;
330	};
331
332	ctimer1: ctimer@29000 {
333		compatible = "nxp,lpc-ctimer";
334		reg = <0x29000 0x1000>;
335		interrupts = <11 0>;
336		status = "disabled";
337		clk-source = <1>;
338		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
339		mode = <0>;
340		input = <0>;
341		prescale = <0>;
342	};
343
344	ctimer2: ctimer@2a000 {
345		compatible = "nxp,lpc-ctimer";
346		reg = <0x2a000 0x1000>;
347		interrupts = <39 0>;
348		status = "disabled";
349		clk-source = <1>;
350		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
351		mode = <0>;
352		input = <0>;
353		prescale = <0>;
354	};
355
356	ctimer3: ctimer@2b000 {
357		compatible = "nxp,lpc-ctimer";
358		reg = <0x2b000 0x1000>;
359		interrupts = <13 0>;
360		status = "disabled";
361		clk-source = <1>;
362		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
363		mode = <0>;
364		input = <0>;
365		prescale = <0>;
366	};
367
368	sctimer: pwm@146000 {
369		compatible = "nxp,sctimer-pwm";
370		reg = <0x146000 0x1000>;
371		interrupts = <12 0>;
372		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
373		status = "disabled";
374		prescaler = <8>;
375		#pwm-cells = <3>;
376	};
377
378	mrt0: mrt@2d000 {
379		compatible = "nxp,mrt";
380		reg = <0x2d000 0x100>;
381		interrupts = <9 0>;
382		num-channels = <4>;
383		num-bits = <24>;
384		clocks = <&clkctl1 MCUX_MRT_CLK>;
385		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
386		#address-cells = <1>;
387		#size-cells = <0>;
388
389		mrt0_channel0: mrt0_channel@0 {
390			compatible = "nxp,mrt-channel";
391			reg = <0>;
392			status = "disabled";
393		};
394		mrt0_channel1: mrt0_channel@1 {
395			compatible = "nxp,mrt-channel";
396			reg = <1>;
397			status = "disabled";
398		};
399		mrt0_channel2: mrt0_channel@2 {
400			compatible = "nxp,mrt-channel";
401			reg = <2>;
402			status = "disabled";
403		};
404		mrt0_channel3: mrt0_channel@3 {
405			compatible = "nxp,mrt-channel";
406			reg = <3>;
407			status = "disabled";
408		};
409	};
410
411	mrt1: mrt@3f000 {
412		compatible = "nxp,mrt";
413		reg = <0x3f000 0x100>;
414		interrupts = <23 0>;
415		num-channels = <4>;
416		num-bits = <24>;
417		clocks = <&clkctl1 MCUX_FREEMRT_CLK>;
418		resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
419		#address-cells = <1>;
420		#size-cells = <0>;
421
422		mrt1_channel0: mrt1_channel@0 {
423			compatible = "nxp,mrt-channel";
424			reg = <0>;
425			status = "disabled";
426		};
427		mrt1_channel1: mrt1_channel@1 {
428			compatible = "nxp,mrt-channel";
429			reg = <1>;
430			status = "disabled";
431		};
432		mrt1_channel2: mrt1_channel@2 {
433			compatible = "nxp,mrt-channel";
434			reg = <2>;
435			status = "disabled";
436		};
437		mrt1_channel3: mrt1_channel@3 {
438			compatible = "nxp,mrt-channel";
439			reg = <3>;
440			status = "disabled";
441		};
442	};
443
444	dmic0: dmic@121000 {
445		#address-cells=<1>;
446		#size-cells=<0>;
447		compatible = "nxp,dmic";
448		reg = <0x121000 0x1000>;
449		interrupts = <25 0>;
450		status = "disabled";
451		clocks = <&clkctl1 MCUX_DMIC_CLK>;
452
453		pdmc0: dmic-channel@0 {
454			reg = <0>;
455			compatible = "nxp,dmic-channel";
456			dmas = <&dma0 16>;
457			status = "disabled";
458		};
459
460		pdmc1: dmic-channel@1 {
461			reg = <1>;
462			compatible = "nxp,dmic-channel";
463			dmas = <&dma0 17>;
464			status = "disabled";
465		};
466
467		pdmc2: dmic-channel@2 {
468			reg = <2>;
469			compatible = "nxp,dmic-channel";
470			dmas = <&dma0 18>;
471			status = "disabled";
472		};
473
474		pdmc3: dmic-channel@3 {
475			reg = <3>;
476			compatible = "nxp,dmic-channel";
477			dmas = <&dma0 19>;
478			status = "disabled";
479		};
480	};
481
482	gau {
483		ranges = <>;
484		#address-cells = <1>;
485		#size-cells = <1>;
486
487		adc0: gau_adc0@38000 {
488			compatible = "nxp,gau-adc";
489			reg = <0x38000 0x100>;
490			interrupts = <112 0>;
491			status = "disabled";
492			#io-channel-cells = <1>;
493		};
494
495		adc1: gau_adc1@38100 {
496			compatible = "nxp,gau-adc";
497			reg = <0x38100 0x100>;
498			interrupts = <111 0>;
499			status = "disabled";
500			#io-channel-cells = <1>;
501		};
502
503		dac0: dac@38200 {
504			compatible = "nxp,gau-dac";
505			reg = <0x38200 0x30>;
506			interrupts = <108 0>;
507			status = "disabled";
508			#io-channel-cells = <0>;
509		};
510	};
511
512	os_timer: timers@13b000 {
513		compatible = "nxp,os-timer";
514		reg = <0x13b000 0x1000>;
515		interrupts = <41 0>;
516		status = "disabled";
517	};
518
519	nbu: nbu {
520		compatible = "nxp,nbu";
521		interrupts = <90 2>, <82 2>;
522		interrupt-names = "nbu_rx_int", "wakeup_int";
523	};
524
525	hci: hci_ble {
526		compatible = "nxp,hci-ble";
527	};
528
529	hdlc_rcp_if: hdlc_rcp_if {
530		compatible = "nxp,hdlc-rcp-if";
531		interrupts = <90 2>, <82 2>;
532		interrupt-names = "hdlc_rcp_if_int", "wakeup_int";
533	};
534
535	enet: enet@138000 {
536		compatible = "nxp,enet";
537		reg = <0x138000 0x700>;
538		clocks = <&clkctl1 MCUX_ENET_CLK>;
539		enet_mac: ethernet {
540			compatible = "nxp,enet-mac";
541			interrupts = <115 0>;
542			interrupt-names = "COMMON";
543			nxp,mdio = <&enet_mdio>;
544			nxp,ptp-clock = <&enet_ptp_clock>;
545			status = "disabled";
546		};
547		enet_mdio: mdio {
548			compatible = "nxp,enet-mdio";
549			status = "disabled";
550			#address-cells = <1>;
551			#size-cells = <0>;
552		};
553		enet_ptp_clock: ptp-clock {
554			compatible = "nxp,enet-ptp-clock";
555			interrupts = <116 0>;
556			status = "disabled";
557			clocks = <&clkctl1 MCUX_ENET_PLL>;
558		};
559	};
560};
561
562&flexspi {
563	compatible = "nxp,imx-flexspi";
564	status = "disabled";
565	interrupts = <42 0>;
566	#address-cells = <1>;
567	#size-cells = <0>;
568	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
569};
570
571&nvic {
572	arm,num-irq-priority-bits = <3>;
573};
574