/*
 * Copyright 2022-2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include <dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
#include <dt-bindings/adc/nxp,gau-adc.h>
#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>

/ {
	chosen {
		zephyr,entropy = &trng;
		zephyr,nbu = &nbu;
		zephyr,bt-hci = &hci;
		zephyr,hdlc-rcp-if = &hdlc_rcp_if;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m33f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;
			cpu-power-states = <&idle &suspend>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
			};
		};

		power-states {
			/* Idle mode maps to Power Mode 1 */
			idle: idle {
				compatible = "zephyr,power-state";
				power-state-name = "runtime-idle";
				min-residency-us = <0>;
				exit-latency-us = <0>;
			};
			/* Suspend mode maps to Power Mode 2 */
			suspend: suspend {
				compatible = "nxp,pdcfg-power", "zephyr,power-state";
				power-state-name = "suspend-to-idle";
				min-residency-us = <500>;
				exit-latency-us = <120>;
				deep-sleep-config = <0x180000>,
							<0x0>,
							<0x4>,
							<0x100>,
							<0x0>;
			};
		};
	};

	smu1: sram@41380000 {
		ranges = <0x0 0x41380000 DT_SIZE_K(510)>;
	};

	smu2: sram@443C0000 {
		ranges = <0x0 0x443C0000 DT_SIZE_K(140)>;
	};

};

&sram {
	#address-cells = <1>;
	#size-cells = <1>;

	sram_data: memory@40000 {
		compatible = "mmio-sram";
		reg = <0x40000 DT_SIZE_K(960)>;
	};

	sram_code: memory@0 {
		compatible = "mmio-sram";
		reg = <0x00000000 DT_SIZE_K(256)>;
	};
};

&smu1 {
	#address-cells = <1>;
	#size-cells = <1>;

	smu1_data: memory@0 {
		compatible = "zephyr,memory-region","mmio-sram";
		reg = <0x0 DT_SIZE_K(510)>;
		zephyr,memory-region = "SMU1";
		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
	};
};

&smu2 {
	#address-cells = <1>;
	#size-cells = <1>;

	smu2_data: memory@0 {
		compatible = "zephyr,memory-region","mmio-sram";
		reg = <0x0 DT_SIZE_K(140)>;
		zephyr,memory-region = "SMU2";
		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
	};
};

&peripheral {
	#address-cells = <1>;
	#size-cells = <1>;

	flexspi: spi@134000 {
		reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
	};

	clkctl0: clkctl@1000 {
		/* FIXME This chip does NOT have a syscon */
		compatible = "nxp,lpc-syscon";
		reg = <0x1000 0x1000>;
		#clock-cells = <1>;
	};

	pinctrl: mci_iomux@4000 {
		compatible = "nxp,mci-io-mux";
		reg = <0x4000 0x1000>;
		status = "okay";
	};

	clkctl1: clkctl@21000 {
		/* FIXME This chip does NOT have a syscon */
		compatible = "nxp,lpc-syscon";
		reg = <0x21000 0x1000>;
		#clock-cells = <1>;
	};

	rstctl0: reset@0 {
		compatible = "nxp,rstctl";
		reg = <0x0 0x80>;
		#reset-cells = <1>;
	};

	rstctl1: reset@20000 {
		compatible = "nxp,rstctl";
		reg = <0x20000 0x80>;
		#reset-cells = <1>;
	};

	pmu: pmu@31000 {
		reg = <0x31000 0x130>;
		compatible = "nxp,rw-pmu";
		pin0: pin0 {
			compatible = "nxp,aon-wakeup-pin";
			interrupts = <100 0>;
			status = "disabled";
		};
		pin1: pin1 {
			compatible = "nxp,aon-wakeup-pin";
			interrupts = <101 0>;
			status = "disabled";
		};
	};

	trng: random@14000 {
		compatible = "nxp,kinetis-trng";
		reg = <0x14000 0x1000>;
		status = "okay";
		interrupts = <123 0>;
	};

	wwdt: watchdog@e000 {
		compatible = "nxp,lpc-wwdt";
		reg = <0xe000 0x1000>;
		interrupts = <0 0>;
		status = "disabled";
		clk-divider = <1>;
	};

	hsgpio: hsgpio@100000 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;

		hsgpio0: gpio@0 {
			compatible = "nxp,lpc-gpio-port";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			int-source = "pint";
		};

		hsgpio1: gpio@1 {
			compatible = "nxp,lpc-gpio-port";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <1>;
			int-source = "pint";
		};
	};

	usb_otg: usbotg@145000 {
		compatible = "nxp,ehci";
		reg = <0x145000 0x200>;
		interrupts = <50 1>;
		interrupt-names = "usb_otg";
		num-bidir-endpoints = <8>;
		status = "disabled";
	};

	flexcomm0: flexcomm@106000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x106000 0x1000>;
		interrupts = <14 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
		dmas = <&dma0 0>, <&dma0 1>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm1: flexcomm@107000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x107000 0x1000>;
		interrupts = <15 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
		dmas = <&dma0 2>, <&dma0 3>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm2: flexcomm@108000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x108000 0x1000>;
		interrupts = <16 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
		dmas = <&dma0 4>, <&dma0 5>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm3: flexcomm@109000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x109000 0x1000>;
		interrupts = <17 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
		dmas = <&dma0 6>, <&dma0 7>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	flexcomm14: flexcom@126000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x126000 0x2000>;
		interrupts = <20 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM14_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
		dmas = <&dma0 26>, <&dma0 27>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	aon_soc_ctrl: aon_soc_ctrl@5000800 {
		compatible = "nxp,rw-soc-ctrl";
		reg = <0x5000800 0x1000>;
		status = "okay";
	};

	soc_ctrl: soc_ctrl@5001000 {
		compatible = "nxp,rw-soc-ctrl";
		reg = <0x5001000 0x1000>;
		status = "okay";
	};

	pint: pint@25000 {
		compatible = "nxp,pint";
		reg = <0x25000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#address-cells = <0>;
		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
			<35 2>, <36 2>, <37 2>, <38 2>;
		num-lines = <8>;
		num-inputs = <64>;
	};

	imu: nxp_wifi {
		compatible = "nxp,wifi";
		/* first index is the imu interrupt, the second is the wakeup done interrupt */
		interrupts = <72 2>, <64 2>;
	};

	dma0: dma-controller@104000 {
		compatible = "nxp,lpc-dma";
		reg = <0x104000 0x1000>;
		interrupts = <1 0>;
		status = "disabled";
		#dma-cells = <1>;
		dma-channels = <33>;
	};

	lcdic: lcdic@128000 {
		compatible = "nxp,lcdic";
		reg = <0x128000 0x52>;
		interrupts = <61 0>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clkctl1 MCUX_LCDIC_CLK>;
		dmas = <&dma0 0>;
	};

	ctimer0: ctimer@28000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x28000 0x1000>;
		interrupts = <10 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer1: ctimer@29000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x29000 0x1000>;
		interrupts = <11 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer2: ctimer@2a000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2a000 0x1000>;
		interrupts = <39 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer3: ctimer@2b000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2b000 0x1000>;
		interrupts = <13 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	sctimer: pwm@146000 {
		compatible = "nxp,sctimer-pwm";
		reg = <0x146000 0x1000>;
		interrupts = <12 0>;
		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
		status = "disabled";
		prescaler = <8>;
		#pwm-cells = <3>;
	};

	mrt0: mrt@2d000 {
		compatible = "nxp,mrt";
		reg = <0x2d000 0x100>;
		interrupts = <9 0>;
		num-channels = <4>;
		num-bits = <24>;
		clocks = <&clkctl1 MCUX_MRT_CLK>;
		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
		#address-cells = <1>;
		#size-cells = <0>;

		mrt0_channel0: mrt0_channel@0 {
			compatible = "nxp,mrt-channel";
			reg = <0>;
			status = "disabled";
		};
		mrt0_channel1: mrt0_channel@1 {
			compatible = "nxp,mrt-channel";
			reg = <1>;
			status = "disabled";
		};
		mrt0_channel2: mrt0_channel@2 {
			compatible = "nxp,mrt-channel";
			reg = <2>;
			status = "disabled";
		};
		mrt0_channel3: mrt0_channel@3 {
			compatible = "nxp,mrt-channel";
			reg = <3>;
			status = "disabled";
		};
	};

	mrt1: mrt@3f000 {
		compatible = "nxp,mrt";
		reg = <0x3f000 0x100>;
		interrupts = <23 0>;
		num-channels = <4>;
		num-bits = <24>;
		clocks = <&clkctl1 MCUX_FREEMRT_CLK>;
		resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
		#address-cells = <1>;
		#size-cells = <0>;

		mrt1_channel0: mrt1_channel@0 {
			compatible = "nxp,mrt-channel";
			reg = <0>;
			status = "disabled";
		};
		mrt1_channel1: mrt1_channel@1 {
			compatible = "nxp,mrt-channel";
			reg = <1>;
			status = "disabled";
		};
		mrt1_channel2: mrt1_channel@2 {
			compatible = "nxp,mrt-channel";
			reg = <2>;
			status = "disabled";
		};
		mrt1_channel3: mrt1_channel@3 {
			compatible = "nxp,mrt-channel";
			reg = <3>;
			status = "disabled";
		};
	};

	dmic0: dmic@121000 {
		#address-cells=<1>;
		#size-cells=<0>;
		compatible = "nxp,dmic";
		reg = <0x121000 0x1000>;
		interrupts = <25 0>;
		status = "disabled";
		clocks = <&clkctl1 MCUX_DMIC_CLK>;

		pdmc0: dmic-channel@0 {
			reg = <0>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 16>;
			status = "disabled";
		};

		pdmc1: dmic-channel@1 {
			reg = <1>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 17>;
			status = "disabled";
		};

		pdmc2: dmic-channel@2 {
			reg = <2>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 18>;
			status = "disabled";
		};

		pdmc3: dmic-channel@3 {
			reg = <3>;
			compatible = "nxp,dmic-channel";
			dmas = <&dma0 19>;
			status = "disabled";
		};
	};

	gau {
		ranges = <>;
		#address-cells = <1>;
		#size-cells = <1>;

		adc0: gau_adc0@38000 {
			compatible = "nxp,gau-adc";
			reg = <0x38000 0x100>;
			interrupts = <112 0>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		adc1: gau_adc1@38100 {
			compatible = "nxp,gau-adc";
			reg = <0x38100 0x100>;
			interrupts = <111 0>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		dac0: dac@38200 {
			compatible = "nxp,gau-dac";
			reg = <0x38200 0x30>;
			interrupts = <108 0>;
			status = "disabled";
			#io-channel-cells = <0>;
		};
	};

	os_timer: timers@13b000 {
		compatible = "nxp,os-timer";
		reg = <0x13b000 0x1000>;
		interrupts = <41 0>;
		status = "disabled";
	};

	nbu: nbu {
		compatible = "nxp,nbu";
		interrupts = <90 2>, <82 2>;
		interrupt-names = "nbu_rx_int", "wakeup_int";
	};

	hci: hci_ble {
		compatible = "nxp,hci-ble";
	};

	hdlc_rcp_if: hdlc_rcp_if {
		compatible = "nxp,hdlc-rcp-if";
		interrupts = <90 2>, <82 2>;
		interrupt-names = "hdlc_rcp_if_int", "wakeup_int";
	};

	enet: enet@138000 {
		compatible = "nxp,enet";
		reg = <0x138000 0x700>;
		clocks = <&clkctl1 MCUX_ENET_CLK>;
		enet_mac: ethernet {
			compatible = "nxp,enet-mac";
			interrupts = <115 0>;
			interrupt-names = "COMMON";
			nxp,mdio = <&enet_mdio>;
			nxp,ptp-clock = <&enet_ptp_clock>;
			status = "disabled";
		};
		enet_mdio: mdio {
			compatible = "nxp,enet-mdio";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
		enet_ptp_clock: ptp-clock {
			compatible = "nxp,enet-ptp-clock";
			interrupts = <116 0>;
			status = "disabled";
			clocks = <&clkctl1 MCUX_ENET_PLL>;
		};
	};
};

&flexspi {
	compatible = "nxp,imx-flexspi";
	status = "disabled";
	interrupts = <42 0>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};