1/*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/i2c/i2c.h>
10
11/ {
12	aliases {
13		watchdog0 = &wdog;
14	};
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			reg = <0>;
23		};
24	};
25
26	/* Dummy pinctrl node, filled with pin mux options at board level */
27	pinctrl: pinctrl {
28		compatible = "nxp,port-pinctrl";
29		status = "okay";
30	};
31
32	soc {
33		interrupt-parent = <&nvic>;
34
35		mpu: mpu@4000d000 {
36			compatible = "nxp,sysmpu";
37			reg = <0x4000d000 0x1000>;
38			status = "disabled";
39		};
40
41		ftfc: flash-controller@40020000 {
42			compatible = "nxp,kinetis-ftfc";
43			reg = <0x40020000 0x1000>;
44			interrupts = <18 0>, <19 0>, <21 0>;
45			interrupt-names = "command-complete", "read-collision", "double-bit";
46			#address-cells = <1>;
47			#size-cells = <1>;
48			status = "disabled";
49		};
50
51		flexcan0: can@40024000 {
52			compatible = "nxp,flexcan-fd", "nxp,flexcan";
53			reg = <0x40024000 0x1000>;
54			clocks = <&clock NXP_S32_FLEXCAN0_CLK>;
55			clk-source = <1>;
56			status = "disabled";
57		};
58
59		flexcan1: can@40025000 {
60			compatible = "nxp,flexcan-fd", "nxp,flexcan";
61			reg = <0x40025000 0x1000>;
62			clk-source = <1>;
63			status = "disabled";
64		};
65
66		flexcan2: can@4002b000 {
67			compatible = "nxp,flexcan-fd", "nxp,flexcan";
68			reg = <0x4002b000 0x1000>;
69			clk-source = <1>;
70			status = "disabled";
71		};
72
73		lpspi0: spi@4002c000 {
74			compatible = "nxp,lpspi";
75			reg = <0x4002c000 0x1000>;
76			interrupts = <26 0>;
77			clocks = <&clock NXP_S32_LPSPI0_CLK>;
78			#address-cells = <1>;
79			#size-cells = <0>;
80			tx-fifo-size = <4>;
81			rx-fifo-size = <4>;
82			status = "disabled";
83		};
84
85		lpspi1: spi@4002d000 {
86			compatible = "nxp,lpspi";
87			reg = <0x4002d000 0x1000>;
88			interrupts = <27 0>;
89			#address-cells = <1>;
90			#size-cells = <0>;
91			tx-fifo-size = <4>;
92			rx-fifo-size = <4>;
93			status = "disabled";
94		};
95
96		lpspi2: spi@4002e000 {
97			compatible = "nxp,lpspi";
98			reg = <0x4002e000 0x1000>;
99			interrupts = <28 0>;
100			#address-cells = <1>;
101			#size-cells = <0>;
102			tx-fifo-size = <4>;
103			rx-fifo-size = <4>;
104			status = "disabled";
105		};
106
107		porta: pinmux@40049000 {
108			compatible = "nxp,port-pinmux";
109			reg = <0x40049000 0x1000>;
110			clocks = <&clock NXP_S32_PORTA_CLK>;
111		};
112
113		portb: pinmux@4004a000 {
114			compatible = "nxp,port-pinmux";
115			reg = <0x4004a000 0x1000>;
116			clocks = <&clock NXP_S32_PORTB_CLK>;
117		};
118
119		portc: pinmux@4004b000 {
120			compatible = "nxp,port-pinmux";
121			reg = <0x4004b000 0x1000>;
122			clocks = <&clock NXP_S32_PORTC_CLK>;
123		};
124
125		portd: pinmux@4004c000 {
126			compatible = "nxp,port-pinmux";
127			reg = <0x4004c000 0x1000>;
128			clocks = <&clock NXP_S32_PORTD_CLK>;
129		};
130
131		porte: pinmux@4004d000 {
132			compatible = "nxp,port-pinmux";
133			reg = <0x4004d000 0x1000>;
134			clocks = <&clock NXP_S32_PORTE_CLK>;
135		};
136
137		wdog: watchdog@40052000 {
138			compatible = "nxp,wdog32";
139			reg = <0x40052000 0x1000>;
140			interrupts = <22 0>;
141			clocks = <&clock NXP_S32_LPO_128K_CLK>;
142			clk-source = <1>;
143			clk-divider = <256>;
144		};
145
146		clock: clock-controller@40064000 {
147			compatible = "nxp,s32-clock";
148			reg = <0x40064000 0x1000>, <0x40065000 0x1000>;
149			#clock-cells = <1>;
150			status = "okay";
151		};
152
153		lpi2c0: i2c@40066000 {
154			compatible = "nxp,lpi2c";
155			clock-frequency = <I2C_BITRATE_STANDARD>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158			reg = <0x40066000 0x1000>;
159			interrupts = <24 0>;
160			clocks = <&clock NXP_S32_LPI2C0_CLK>;
161			status = "disabled";
162		};
163
164		lpi2c1: i2c@40067000 {
165			compatible = "nxp,lpi2c";
166			clock-frequency = <I2C_BITRATE_STANDARD>;
167			#address-cells = <1>;
168			#size-cells = <0>;
169			reg = <0x40067000 0x1000>;
170			interrupts = <25 0>;
171			status = "disabled";
172		};
173
174		lpuart0: uart@4006a000 {
175			compatible = "nxp,lpuart";
176			reg = <0x4006a000 0x1000>;
177			interrupts = <31 0>;
178			clocks = <&clock NXP_S32_LPUART0_CLK>;
179			status = "disabled";
180		};
181
182		lpuart1: uart@4006b000 {
183			compatible = "nxp,lpuart";
184			reg = <0x4006b000 0x1000>;
185			interrupts = <33 0>;
186			clocks = <&clock NXP_S32_LPUART1_CLK>;
187			status = "disabled";
188		};
189
190		lpuart2: uart@4006c000 {
191			compatible = "nxp,lpuart";
192			reg = <0x4006c000 0x1000>;
193			interrupts = <35 0>;
194			status = "disabled";
195		};
196
197		gpioa: gpio@400ff000 {
198			compatible = "nxp,kinetis-gpio";
199			reg = <0x400ff000 0x40>;
200			interrupts = <59 2>;
201			gpio-controller;
202			#gpio-cells = <2>;
203			nxp,kinetis-port = <&porta>;
204			status = "disabled";
205		};
206
207		gpiob: gpio@400ff040 {
208			compatible = "nxp,kinetis-gpio";
209			reg = <0x400ff040 0x40>;
210			interrupts = <60 2>;
211			gpio-controller;
212			#gpio-cells = <2>;
213			nxp,kinetis-port = <&portb>;
214			status = "disabled";
215		};
216
217		gpioc: gpio@400ff080 {
218			compatible = "nxp,kinetis-gpio";
219			reg = <0x400ff080 0x40>;
220			interrupts = <61 2>;
221			gpio-controller;
222			#gpio-cells = <2>;
223			nxp,kinetis-port = <&portc>;
224			status = "disabled";
225		};
226
227		gpiod: gpio@400ff0c0 {
228			compatible = "nxp,kinetis-gpio";
229			reg = <0x400ff0c0 0x40>;
230			interrupts = <62 2>;
231			gpio-controller;
232			#gpio-cells = <2>;
233			nxp,kinetis-port = <&portd>;
234			status = "disabled";
235		};
236
237		gpioe: gpio@400ff100 {
238			compatible = "nxp,kinetis-gpio";
239			reg = <0x400ff100 0x40>;
240			interrupts = <63 2>;
241			gpio-controller;
242			#gpio-cells = <2>;
243			nxp,kinetis-port = <&porte>;
244			status = "disabled";
245		};
246
247		ftm0: ftm@40038000 {
248			compatible = "nxp,ftm";
249			reg = <0x40038000 0x1000>;
250			interrupts = <99 0>, <100 0>, <101 0>, <102 0>, <104 0>;
251			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
252			clocks = <&clock NXP_S32_CORE_CLK>;
253			prescaler = <1>;
254			status = "disabled";
255		};
256
257		ftm1: ftm@40039000 {
258			compatible = "nxp,ftm";
259			reg = <0x40039000 0x1000>;
260			interrupts = <105 0>, <106 0>, <107 0>, <108 0>, <110 0>;
261			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
262			clocks = <&clock NXP_S32_CORE_CLK>;
263			prescaler = <1>;
264			status = "disabled";
265		};
266
267		ftm2: ftm@4003a000 {
268			compatible = "nxp,ftm";
269			reg = <0x4003a000 0x1000>;
270			interrupts = <111 0>, <112 0>, <113 0>, <114 0>, <116 0>;
271			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
272			clocks = <&clock NXP_S32_CORE_CLK>;
273			prescaler = <1>;
274			status = "disabled";
275		};
276
277		ftm3: ftm@40026000 {
278			compatible = "nxp,ftm";
279			reg = <0x40026000 0x1000>;
280			interrupts = <117 0>, <118 0>, <119 0>, <120 0>, <122 0>;
281			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
282			clocks = <&clock NXP_S32_CORE_CLK>;
283			prescaler = <1>;
284			status = "disabled";
285		};
286
287		ftm4: ftm@4006e000 {
288			compatible = "nxp,ftm";
289			reg = <0x4006e000 0x1000>;
290			interrupts = <123 0>, <124 0>, <125 0>, <126 0>, <128 0>;
291			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
292			clocks = <&clock NXP_S32_CORE_CLK>;
293			prescaler = <1>;
294			status = "disabled";
295		};
296
297		ftm5: ftm@4006f000 {
298			compatible = "nxp,ftm";
299			reg = <0x4006f000 0x1000>;
300			interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <134 0>;
301			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
302			clocks = <&clock NXP_S32_CORE_CLK>;
303			prescaler = <1>;
304			status = "disabled";
305		};
306
307		ftm6: ftm@40070000 {
308			compatible = "nxp,ftm";
309			reg = <0x40070000 0x1000>;
310			interrupts = <135 0>, <136 0>, <137 0>, <138 0>, <140 0>;
311			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
312			clocks = <&clock NXP_S32_CORE_CLK>;
313			prescaler = <1>;
314			status = "disabled";
315		};
316
317		ftm7: ftm@40071000 {
318			compatible = "nxp,ftm";
319			reg = <0x40071000 0x1000>;
320			interrupts = <141 0>, <142 0>, <143 0>, <144 0>, <146 0>;
321			interrupt-names = "0-1", "2-3", "4-5", "6-7", "overflow";
322			clocks = <&clock NXP_S32_CORE_CLK>;
323			prescaler = <1>;
324			status = "disabled";
325		};
326
327		rtc: rtc@4003d000 {
328			compatible = "nxp,rtc";
329			reg = <0x4003d000 0x1000>;
330			interrupts = <46 0>, <47 0>;
331			interrupt-names = "alarm", "seconds";
332			clock-frequency = <32000>;
333			prescaler = <32000>;
334		};
335
336		adc0: adc@4003b000 {
337			compatible = "nxp,adc12";
338			reg = <0x4003b000 0x1000>;
339			interrupts = <39 0>;
340			clk-source = <0>;
341			clk-divider = <1>;
342			clocks = <&clock NXP_S32_ADC0_CLK>;
343			#io-channel-cells = <1>;
344			status = "disabled";
345		};
346
347		adc1: adc@40027000 {
348			compatible = "nxp,adc12";
349			reg = <0x40027000 0x1000>;
350			interrupts = <40 0>;
351			clk-source = <0>;
352			clk-divider = <1>;
353			clocks = <&clock NXP_S32_ADC1_CLK>;
354			#io-channel-cells = <1>;
355			status = "disabled";
356		};
357	};
358};
359