1 /*
2 * Copyright (c) 2024 Michael Hope
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/clock_control.h>
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/drivers/gpio/gpio_utils.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/irq.h>
12
13 #include <ch32fun.h>
14
15 #define DT_DRV_COMPAT wch_gpio
16
17 struct gpio_ch32v00x_config {
18 struct gpio_driver_config common;
19 GPIO_TypeDef *regs;
20 const struct device *clock_dev;
21 uint8_t clock_id;
22 };
23
24 struct gpio_ch32v00x_data {
25 struct gpio_driver_data common;
26 };
27
gpio_ch32v00x_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)28 static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
29 {
30 const struct gpio_ch32v00x_config *config = dev->config;
31 GPIO_TypeDef *regs = config->regs;
32 uint32_t cnf_mode;
33 uint32_t bshr = 0;
34
35 if ((flags & GPIO_OUTPUT) != 0) {
36 cnf_mode = 0x01;
37 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
38 bshr = 1 << pin;
39 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
40 bshr = 1 << (16 + pin);
41 }
42 } else if ((flags & GPIO_INPUT) != 0) {
43 if ((flags & GPIO_PULL_UP) != 0) {
44 cnf_mode = GPIO_CFGLR_IN_PUPD;
45 bshr = 1 << pin;
46 } else if ((flags & GPIO_PULL_DOWN) != 0) {
47 cnf_mode = GPIO_CFGLR_IN_PUPD;
48 bshr = 1 << (16 + pin);
49 } else {
50 cnf_mode = GPIO_CFGLR_IN_FLOAT;
51 }
52 } else {
53 cnf_mode = 0x00;
54 }
55
56 if (pin < 8) {
57 regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin));
58 } else {
59 regs->CFGHR =
60 (regs->CFGHR & ~(0x0F << ((pin - 8) * 4))) | (cnf_mode << ((pin - 8) * 4));
61 }
62 regs->BSHR = bshr;
63
64 return 0;
65 }
66
gpio_ch32v00x_port_get_raw(const struct device * dev,uint32_t * value)67 static int gpio_ch32v00x_port_get_raw(const struct device *dev, uint32_t *value)
68 {
69 const struct gpio_ch32v00x_config *config = dev->config;
70
71 *value = config->regs->INDR;
72
73 return 0;
74 }
75
gpio_ch32v00x_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)76 static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask,
77 uint32_t value)
78 {
79 const struct gpio_ch32v00x_config *config = dev->config;
80
81 config->regs->BSHR = ((~value & mask) << 16) | (value & mask);
82
83 return 0;
84 }
85
gpio_ch32v00x_port_set_bits_raw(const struct device * dev,uint32_t pins)86 static int gpio_ch32v00x_port_set_bits_raw(const struct device *dev, uint32_t pins)
87 {
88 const struct gpio_ch32v00x_config *config = dev->config;
89
90 config->regs->BSHR = pins;
91
92 return 0;
93 }
94
gpio_ch32v00x_port_clear_bits_raw(const struct device * dev,uint32_t pins)95 static int gpio_ch32v00x_port_clear_bits_raw(const struct device *dev, uint32_t pins)
96 {
97 const struct gpio_ch32v00x_config *config = dev->config;
98
99 config->regs->BCR = pins;
100
101 return 0;
102 }
103
gpio_ch32v00x_port_toggle_bits(const struct device * dev,uint32_t pins)104 static int gpio_ch32v00x_port_toggle_bits(const struct device *dev, uint32_t pins)
105 {
106 const struct gpio_ch32v00x_config *config = dev->config;
107 uint32_t changed = (config->regs->OUTDR ^ pins) & pins;
108
109 config->regs->BSHR = (changed & pins) | (~changed & pins) << 16;
110
111 return 0;
112 }
113
114 static DEVICE_API(gpio, gpio_ch32v00x_driver_api) = {
115 .pin_configure = gpio_ch32v00x_configure,
116 .port_get_raw = gpio_ch32v00x_port_get_raw,
117 .port_set_masked_raw = gpio_ch32v00x_port_set_masked_raw,
118 .port_set_bits_raw = gpio_ch32v00x_port_set_bits_raw,
119 .port_clear_bits_raw = gpio_ch32v00x_port_clear_bits_raw,
120 .port_toggle_bits = gpio_ch32v00x_port_toggle_bits,
121 };
122
gpio_ch32v00x_init(const struct device * dev)123 static int gpio_ch32v00x_init(const struct device *dev)
124 {
125 const struct gpio_ch32v00x_config *config = dev->config;
126
127 clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id);
128
129 return 0;
130 }
131
132 #define GPIO_CH32V00X_INIT(idx) \
133 static const struct gpio_ch32v00x_config gpio_ch32v00x_##idx##_config = { \
134 .common = \
135 { \
136 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
137 }, \
138 .regs = (GPIO_TypeDef *)DT_INST_REG_ADDR(idx), \
139 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
140 .clock_id = DT_INST_CLOCKS_CELL(idx, id), \
141 }; \
142 \
143 static struct gpio_ch32v00x_data gpio_ch32v00x_##idx##_data; \
144 \
145 DEVICE_DT_INST_DEFINE(idx, gpio_ch32v00x_init, NULL, &gpio_ch32v00x_##idx##_data, \
146 &gpio_ch32v00x_##idx##_config, PRE_KERNEL_1, \
147 CONFIG_GPIO_INIT_PRIORITY, &gpio_ch32v00x_driver_api);
148
149 DT_INST_FOREACH_STATUS_OKAY(GPIO_CH32V00X_INIT)
150
