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Searched defs:base_addr (Results 1 – 25 of 36) sorted by relevance

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/Zephyr-Core-3.7.0/drivers/gpio/
Dgpio_dw.c38 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read()
43 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write()
49 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit()
59 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read()
64 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write()
70 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit()
81 static inline int dw_base_to_block_base(uint32_t base_addr) in dw_base_to_block_base()
86 static inline int dw_derive_port_from_base(uint32_t base_addr) in dw_derive_port_from_base()
97 static inline uint32_t dw_get_ext_port(uint32_t base_addr) in dw_get_ext_port()
121 static inline uint32_t dw_get_data_port(uint32_t base_addr) in dw_get_data_port()
[all …]
Dgpio_xlnx_ps.h39 uint32_t base_addr; member
Dgpio_dw.h31 uint32_t base_addr; member
Dgpio_xlnx_ps_bank.h68 uint32_t base_addr; member
Dgpio_creg_gpio.c29 uint32_t base_addr; member
Dgpio_efinix_sapphire.c39 uint32_t base_addr; member
/Zephyr-Core-3.7.0/tests/drivers/syscon/src/
Dmain.c39 uintptr_t base_addr; in ZTEST() local
53 uintptr_t base_addr; in ZTEST() local
/Zephyr-Core-3.7.0/include/zephyr/drivers/mm/
Drat.h18 #define RAT_CTRL(base_addr, i) (base_addr + 0x20 + 0x10 * (i)) argument
19 #define RAT_BASE(base_addr, i) (base_addr + 0x24 + 0x10 * (i)) argument
20 #define RAT_TRANS_L(base_addr, i) (base_addr + 0x28 + 0x10 * (i)) argument
21 #define RAT_TRANS_H(base_addr, i) (base_addr + 0x2C + 0x10 * (i)) argument
/Zephyr-Core-3.7.0/drivers/bbram/
Dit8xxx2.h16 uintptr_t base_addr; member
Dnpcx.h16 uintptr_t base_addr; member
Dbbram_it8xxx2.c79 uint8_t *base_addr = (uint8_t *)config->base_addr; in bbram_it8xxx2_init() local
Dbbram_stm32.c35 uintptr_t base_addr; member
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.c17 mm_reg_t base_addr; member
27 void clock_agilex5_ll_init(mm_reg_t base_addr) in clock_agilex5_ll_init()
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_cavs.h25 uint32_t base_addr; member
/Zephyr-Core-3.7.0/samples/drivers/led_xec/src/
Dmain.c21 uint32_t base_addr; member
/Zephyr-Core-3.7.0/soc/mediatek/mtk_adsp/
Dmtk_adsp_load.py125 def __init__(self, base_addr): argument
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/common/include/
Dmem_window.h37 uint32_t base_addr; member
/Zephyr-Core-3.7.0/drivers/ethernet/
Dphy_xlnx_gem.c37 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_read()
116 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_write()
/Zephyr-Core-3.7.0/subsys/net/lib/shell/
Ddhcpv4.c20 struct in_addr base_addr; in cmd_net_dhcpv4_server_start() local
/Zephyr-Core-3.7.0/drivers/misc/ethos_u/
Dethos_u.c109 void *base_addr; member
/Zephyr-Core-3.7.0/drivers/flash/
Dflash_ifx_cat1.c24 uint32_t base_addr; member
Dflash_ifx_cat1_qspi.c25 uint32_t base_addr; member
/Zephyr-Core-3.7.0/drivers/i2c/
Di2c_dw.h132 uintptr_t base_addr; member
/Zephyr-Core-3.7.0/drivers/espi/
Despi_mchp_xec_v2.h38 uint32_t base_addr; member
/Zephyr-Core-3.7.0/drivers/peci/
Dpeci_ite_it8xxx2.c95 uintptr_t base_addr; member

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