/Zephyr-Core-3.7.0/drivers/gpio/ |
D | gpio_dw.c | 38 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() 43 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write() 49 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit() 59 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() 64 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write() 70 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit() 81 static inline int dw_base_to_block_base(uint32_t base_addr) in dw_base_to_block_base() 86 static inline int dw_derive_port_from_base(uint32_t base_addr) in dw_derive_port_from_base() 97 static inline uint32_t dw_get_ext_port(uint32_t base_addr) in dw_get_ext_port() 121 static inline uint32_t dw_get_data_port(uint32_t base_addr) in dw_get_data_port() [all …]
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D | gpio_xlnx_ps.h | 39 uint32_t base_addr; member
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D | gpio_dw.h | 31 uint32_t base_addr; member
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D | gpio_xlnx_ps_bank.h | 68 uint32_t base_addr; member
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D | gpio_creg_gpio.c | 29 uint32_t base_addr; member
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D | gpio_efinix_sapphire.c | 39 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/tests/drivers/syscon/src/ |
D | main.c | 39 uintptr_t base_addr; in ZTEST() local 53 uintptr_t base_addr; in ZTEST() local
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/Zephyr-Core-3.7.0/include/zephyr/drivers/mm/ |
D | rat.h | 18 #define RAT_CTRL(base_addr, i) (base_addr + 0x20 + 0x10 * (i)) argument 19 #define RAT_BASE(base_addr, i) (base_addr + 0x24 + 0x10 * (i)) argument 20 #define RAT_TRANS_L(base_addr, i) (base_addr + 0x28 + 0x10 * (i)) argument 21 #define RAT_TRANS_H(base_addr, i) (base_addr + 0x2C + 0x10 * (i)) argument
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/Zephyr-Core-3.7.0/drivers/bbram/ |
D | it8xxx2.h | 16 uintptr_t base_addr; member
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D | npcx.h | 16 uintptr_t base_addr; member
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D | bbram_it8xxx2.c | 79 uint8_t *base_addr = (uint8_t *)config->base_addr; in bbram_it8xxx2_init() local
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D | bbram_stm32.c | 35 uintptr_t base_addr; member
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/Zephyr-Core-3.7.0/drivers/clock_control/ |
D | clock_control_agilex5_ll.c | 17 mm_reg_t base_addr; member 27 void clock_agilex5_ll_init(mm_reg_t base_addr) in clock_agilex5_ll_init()
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/Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
D | intc_cavs.h | 25 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/samples/drivers/led_xec/src/ |
D | main.c | 21 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/soc/mediatek/mtk_adsp/ |
D | mtk_adsp_load.py | 125 def __init__(self, base_addr): argument
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/Zephyr-Core-3.7.0/soc/intel/intel_adsp/common/include/ |
D | mem_window.h | 37 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/drivers/ethernet/ |
D | phy_xlnx_gem.c | 37 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_read() 116 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_write()
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/Zephyr-Core-3.7.0/subsys/net/lib/shell/ |
D | dhcpv4.c | 20 struct in_addr base_addr; in cmd_net_dhcpv4_server_start() local
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/Zephyr-Core-3.7.0/drivers/misc/ethos_u/ |
D | ethos_u.c | 109 void *base_addr; member
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/Zephyr-Core-3.7.0/drivers/flash/ |
D | flash_ifx_cat1.c | 24 uint32_t base_addr; member
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D | flash_ifx_cat1_qspi.c | 25 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/drivers/i2c/ |
D | i2c_dw.h | 132 uintptr_t base_addr; member
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/Zephyr-Core-3.7.0/drivers/espi/ |
D | espi_mchp_xec_v2.h | 38 uint32_t base_addr; member
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/Zephyr-Core-3.7.0/drivers/peci/ |
D | peci_ite_it8xxx2.c | 95 uintptr_t base_addr; member
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