/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/ |
D | MKE14Z4.h | 4617 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/ |
D | MKE15Z4.h | 4618 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/ |
D | MKE12Z7.h | 7577 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/ |
D | MKE16Z4.h | 4616 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/ |
D | MKE13Z7.h | 7579 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/ |
D | MKE17Z7.h | 7581 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/ |
D | MKE14Z7.h | 7181 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/ |
D | MKE15Z7.h | 7183 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/ |
D | MKE16F16.h | 10760 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/ |
D | MKE14F16.h | 9761 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/ |
D | MKE18F16.h | 10765 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/ |
D | K32L2A31A.h | 8525 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/ |
D | K32L2A41A.h | 8525 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/ |
D | K32L3A60_cm0plus.h | 10202 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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D | K32L3A60_cm4.h | 10837 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/ |
D | MCIMX7U5_cm4.h | 13120 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/ |
D | MCIMX7U3_cm4.h | 13119 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/ |
D | MIMX8QM6_ca53.h | 61732 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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D | MIMX8QM6_cm4_core0.h | 76768 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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D | MIMX8QM6_cm4_core1.h | 76768 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/ |
D | MIMX9352_cm33.h | 48003 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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D | MIMX9352_ca55.h | 42800 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/ |
D | MIMX8DX2_cm4.h | 82184 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/ |
D | MIMX8DX1_cm4.h | 82184 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/ |
D | MIMX8QX2_cm4.h | 82185 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
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