| /hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/ |
| D | stm32h5xx_hal_i3c.h | 383 uint32_t DCR; /*!< Device Characteristics Register */ member
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| /hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/ |
| D | stm32h7rsxx_hal_i3c.h | 383 uint32_t DCR; /*!< Device Characteristics Register */ member
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| /hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/ |
| D | stm32n6xx_hal_i3c.h | 383 uint32_t DCR; /*!< Device Characteristics Register */ member
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| /hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
| D | stm32f030x6.h | 382 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f030x8.h | 388 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f031x6.h | 392 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f030xc.h | 394 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f038xx.h | 391 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f070x6.h | 384 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32f070xb.h | 393 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /hal_stm32-latest/stm32cube/stm32f1xx/soc/ |
| D | stm32f101x6.h | 419 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0… member
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| D | stm32f101xb.h | 424 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0… member
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| D | stm32f100xb.h | 467 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0… member
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| D | stm32f100xe.h | 533 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0… member
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| /hal_stm32-latest/stm32cube/stm32l4xx/soc/ |
| D | stm32l422xx.h | 480 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
682 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l412xx.h | 479 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
681 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
| D | stm32l010x8.h | 421 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l010xb.h | 422 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l011xx.h | 436 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l021xx.h | 455 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l010x4.h | 421 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l010x6.h | 421 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l041xx.h | 456 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| D | stm32l081xx.h | 487 …__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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| /hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
| D | stm32wb35xx.h | 425 …__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset… member
625 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ member
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