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Searched defs:Base (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c373 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE]; in ISR() local
397 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE]; in ISR() local
424 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE]; in ISR() local
448 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE]; in ISR() local
475 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE]; in ISR() local
499 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE]; in ISR() local
526 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE]; in ISR() local
550 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE]; in ISR() local
577 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE]; in ISR() local
601 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE]; in ISR() local
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/hal_nxp-latest/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h139 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetDebugMode()
151 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetOutputUpdate()
163 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetOutputUpdate()
173 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetOutputUpdateInstance()
185 static inline void Emios_Pwm_Ip_SetChannelEnable(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetChannelEnable()
198 static inline boolean Emios_Pwm_Ip_GetChannelEnable(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetChannelEnable()
211 static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetUCRegA()
224 …ic inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetUCRegA()
237 static inline void Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetUCRegB()
250 …ic inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetUCRegB()
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/hal_nxp-latest/s32/drivers/s32ze/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h156 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetDebugMode()
168 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetOutputUpdate()
181 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetOutputUpdate()
192 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetOutputUpdateInstance()
204 static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetUCRegA()
218 …ic inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetUCRegA()
232 static inline void Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetUCRegB()
246 …ic inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetUCRegB()
260 …s_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetInternalCounterValue()
276 static inline void Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetFreezeEnable()
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/hal_nxp-latest/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c297 const Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_GetCounterBusMode() local
343 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode() local
410 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmMode() local
476 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwfmb() local
542 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwfm() local
657 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitDeadTimeMode() local
728 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwmcb() local
799 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwmc() local
886 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitEdgePlacementOpwmMode() local
965 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitEdgePlacementOpwmbMode() local
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Pwm/src/
DEmios_Pwm_Ip.c300 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetOutputToNormalOpwfm() local
338 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetOutputToNormalOpwm() local
448 const Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_GetCounterBusMode() local
495 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode() local
563 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmMode() local
630 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwfmb() local
697 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwfm() local
809 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitDeadTimeMode() local
880 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetDutyCycleOpwmcb() local
979 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitEdgePlacementOpwmMode() local
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c368 const GMAC_Type *Base; in Gmac_Ip_ReadTimeStampInfo() local
419 GMAC_Type *Base; in Gmac_Ip_InitDMA() local
488 static void Gmac_Ip_InitSafetyEvents(GMAC_Type *Base, in Gmac_Ip_InitSafetyEvents()
667 static void Gmac_Ip_InitMAC(GMAC_Type *Base, in Gmac_Ip_InitMAC()
860 static void Gmac_Ip_GetTimestamp(const GMAC_Type *Base, in Gmac_Ip_GetTimestamp()
1054 void Gmac_Ip_SetUserAccessAllowed(const GMAC_Type *Base) in Gmac_Ip_SetUserAccessAllowed()
1065 void Gmac_Ip_ClrUserAccessAllowed(const GMAC_Type *Base) in Gmac_Ip_ClrUserAccessAllowed()
1085 GMAC_Type *Base; in Gmac_Ip_Init() local
1237 GMAC_Type *Base; in Gmac_Ip_Deinit() local
1265 const GMAC_Type *Base; in Gmac_Ip_GetPowerState() local
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DGmac_Ip_Hw_Access.c211 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_IrqFSMDPPHandler() local
255 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_MACIRQHandler() local
333 Gmac_Ip_StatusType GMAC_WriteManagementFrame(GMAC_Type * Base, in GMAC_WriteManagementFrame()
385 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_CommonIRQHandler() local
432 GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_SafetyIRQHandler() local
550 void GMAC_AddToHashTable(const GMAC_Type * Base, in GMAC_AddToHashTable()
572 void GMAC_RemoveFromHashTable(const GMAC_Type * Base, in GMAC_RemoveFromHashTable()
592 void GMAC_AddVlanToHashTable(GMAC_Type * Base, in GMAC_AddVlanToHashTable()
613 void GMAC_RemoveVlanFromHashTable(GMAC_Type * Base, in GMAC_RemoveVlanFromHashTable()
634 Gmac_Ip_PowerStateType GMAC_GetPowerState(const GMAC_Type * Base) in GMAC_GetPowerState()
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/hal_nxp-latest/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c262 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_SetBaudrate() local
382 LINFLEXD_Type * Base = Linflexd_Uart_Ip_apBases[Instance]; in Linflexd_Uart_Ip_Init() local
432 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_Deinit() local
544 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_PutData() local
593 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_CompleteSendUsingInterrupts() local
647 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_CompleteReceiveUsingInterrupts() local
724 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_SyncSend() local
786 const LINFLEXD_Type * Base; in Linflexd_Uart_Ip_GetData() local
837 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_SyncReceive() local
1007 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_StartReceiveUsingInterrupts() local
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/hal_nxp-latest/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip_HwAccess.h246 static inline void Linflexd_Uart_Ip_EnterInitMode(LINFLEXD_Type *Base) in Linflexd_Uart_Ip_EnterInitMode()
264 static inline void Linflexd_Uart_Ip_EnterNormalMode(LINFLEXD_Type *Base) in Linflexd_Uart_Ip_EnterNormalMode()
283 static inline void Linflexd_Uart_Ip_SetMode(LINFLEXD_Type *Base, Linflexd_Uart_Ip_ModeType Mode) in Linflexd_Uart_Ip_SetMode()
303 static inline void Linflexd_Uart_Ip_EnableMonitorIdleState(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_EnableMonitorIdleState()
319 static inline void Linflexd_Uart_Ip_EnableTimerReset(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_EnableTimerReset()
344 static inline Linflexd_Uart_Ip_StateType Linflexd_Uart_Ip_GetLinState(const LINFLEXD_Type * Base) in Linflexd_Uart_Ip_GetLinState()
360 static inline void Linflexd_Uart_Ip_SetUartWordLength(LINFLEXD_Type *Base, Linflexd_Uart_Ip_WordLen… in Linflexd_Uart_Ip_SetUartWordLength()
382 static inline void Linflexd_Uart_Ip_SetParityControl(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_SetParityControl()
406 static inline void Linflexd_Uart_Ip_SetParityType(LINFLEXD_Type *Base, Linflexd_Uart_Ip_ParityType … in Linflexd_Uart_Ip_SetParityType()
428 static inline void Linflexd_Uart_Ip_SetTxMode(LINFLEXD_Type *Base, Linflexd_Uart_Ip_RxTxModeType Mo… in Linflexd_Uart_Ip_SetTxMode()
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/hal_nxp-latest/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c259 static uint16 Spi_Ip_WriteCmdFifo(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_WriteCmdFifo()
299 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TransferProcess() local
424 static void Spi_Ip_UpdateCtarAndPushr(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_UpdateCtarAndPushr()
484 static void Spi_Ip_PrepareTransfer(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint16 NbBytes) in Spi_Ip_PrepareTransfer()
593 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_CmdDmaTcdSGInit() local
632 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TxDmaTcdSGInit() local
726 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_RxDmaTcdSGInit() local
907 static void Spi_Ip_DmaConfig(const Spi_Ip_StateStructureType* State,const SPI_Type *Base) in Spi_Ip_DmaConfig()
1058 static void Spi_Ip_DmaAsyncStart(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint32 IrqEn) in Spi_Ip_DmaAsyncStart()
1100 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_WriteTxFifo() local
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/hal_nxp-latest/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Init() local
270 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_EnableChannel() local
282 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_DisableChannel() local
294 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ComparatorTransferEnable() local
307 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ComparatorTransferDisable() local
321 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Deinit() local
479 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ConfigureGlobalTimebase() local
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c1753 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetFDBaudRate() local
1783 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetXLBaudRate() local
1812 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetBaudRate() local
1833 const CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_GetFDBaudRate() local
1851 const CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_GetXLBaudRate() local
1868 const CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_GetBaudRate() local
1885 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetListenOnlyMode() local
1906 const CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_GetListenOnlyMode() local
1924 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetTDCOffsetFD() local
1950 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetTDCOffsetXL() local
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Mcl/src/
DEmios_Mcl_Ip.c169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Init() local
263 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ComparatorTransferEnable() local
276 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ComparatorTransferDisable() local
290 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Deinit() local
442 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_ConfigureGlobalTimebase() local
458 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_SetClockMode() local
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h555 static inline void CanXL_SetXLErrorResponse(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetXLErrorResponse()
565 static inline void CanXL_SetPwmModeEnable(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetPwmModeEnable()
576 static inline boolean CanXL_IsPwmModeEnable(const CANXL_SIC_Type * Base) in CanXL_IsPwmModeEnable()
585 static inline void CanXL_SetPWMPhases(CANXL_SIC_Type * Base, uint8 PWMS, uint8 PWML, uint8 PWMO) in CanXL_SetPWMPhases()
/hal_nxp-latest/mcux/mcux-sdk/components/rtt/RTT/
DSEGGER_RTT_printf.c145 unsigned Base, in _PrintUnsigned()
263 unsigned Base, in _PrintInt()
/hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip_Hw_Access.h215 static inline uint16 GMAC_ReadManagementFrameData(const GMAC_Type * Base) in GMAC_ReadManagementFrameData()
/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip_HwAccess.h171 static inline void Adc_Sar_EnableHighSpeed(ADC_Type * const Base, in Adc_Sar_EnableHighSpeed()
/hal_nxp-latest/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h171 static inline void Adc_Sar_EnableHighSpeed(ADC_Type * const Base, in Adc_Sar_EnableHighSpeed()
/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c4077 static uint64 Clock_Ip_Get_PLL_VCO(const PLLDIG_Type *Base) in Clock_Ip_Get_PLL_VCO()
4158 static uint64 Clock_Ip_Get_LFAST_PLL_VCO(const LFAST_Type *Base) in Clock_Ip_Get_LFAST_PLL_VCO()
4220 static uint64 Clock_Ip_Get_DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint64 Fin) in Clock_Ip_Get_DFS_OUTPUT()
/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Frequency.c1616 static uint32 PLL_VCO(SCG_Type const *Base) in PLL_VCO()
/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c3988 static uint32 Clock_Ip_PLL_VCO(const PLL_Type *Base) in Clock_Ip_PLL_VCO()