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Searched refs:sr (Results 1 – 25 of 44) sorted by relevance

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/Zephyr-latest/lib/heap/
Dheap_stress.c41 static bool rand_alloc_choice(struct z_heap_stress_rec *sr) in rand_alloc_choice() argument
44 if (sr->blocks_alloced == 0) { in rand_alloc_choice()
46 } else if (sr->blocks_alloced >= sr->nblocks) { in rand_alloc_choice()
65 __ASSERT(sr->total_bytes < 0xffffffffU / 100, "too big for u32!"); in rand_alloc_choice()
66 uint32_t full_pct = (100 * sr->bytes_alloced) / sr->total_bytes; in rand_alloc_choice()
67 uint32_t target = sr->target_percent ? sr->target_percent : 1; in rand_alloc_choice()
70 if (full_pct < sr->target_percent) { in rand_alloc_choice()
81 static size_t rand_alloc_size(struct z_heap_stress_rec *sr) in rand_alloc_size() argument
83 ARG_UNUSED(sr); in rand_alloc_size()
94 static size_t rand_free_choice(struct z_heap_stress_rec *sr) in rand_free_choice() argument
[all …]
/Zephyr-latest/arch/arc/core/dsp/
Dswap_dsp_macros.h143 sr r13, [_ARC_V2_DSP_CTRL]
145 sr r13, [_ARC_V2_ACC0_GLO]
147 sr r13, [_ARC_V2_ACC0_GHI]
150 sr r13, [_ARC_V2_DSP_BFLY0]
152 sr r13, [_ARC_V2_DSP_FFT_CTRL]
169 sr r13, [_ARC_V2_AGU_AP0]
171 sr r13, [_ARC_V2_AGU_AP1]
173 sr r13, [_ARC_V2_AGU_AP2]
175 sr r13, [_ARC_V2_AGU_AP3]
177 sr r13, [_ARC_V2_AGU_OS0]
[all …]
/Zephyr-latest/arch/arc/core/
Dreset.S61 sr r0, [_ARC_V2_AUX_IRQ_ACT]
62 sr r0, [_ARC_V2_AUX_IRQ_CTRL]
64 sr r0, [_ARC_V2_AUX_IRQ_HINT]
71 sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
98 sr r2, [_ARC_V2_IC_IVIC]
111 sr r1, [_ARC_V2_DC_IVDC]
134 sr r1, [_ARC_V2_MPU_EN]
144 sr r2, [_ARC_V2_MPU_INDEX]
145 sr r1, [_ARC_V2_MPU_RSTART]
146 sr r1, [_ARC_V2_MPU_REND]
[all …]
Duserspace.S149 sr r0, [_ARC_V2_ERSTATUS]
150 sr r1, [_ARC_V2_ERET]
164 sr r0, [_ARC_V2_ERSEC_STAT]
165 sr r5, [_ARC_V2_SEC_U_SP]
167 sr r5, [_ARC_V2_USER_SP]
228 sr r0,[_ARC_V2_ERSEC_STAT]
231 sr r0,[_ARC_V2_ERSTATUS]
234 sr r0,[_ARC_V2_ERET]
Dfast_irq.S106 sr sp, [_ARC_V2_USER_SP]
139 sr r24, [_ARC_V2_LP_START]
140 sr r25, [_ARC_V2_LP_END]
267 sr r0, [_ARC_V2_STATUS32_P0]
287 sr ilink, [_ARC_V2_STATUS32_P0]
Dfault_s.S227 sr r0, [_ARC_V2_ERSTATUS]
230 sr r0, [_ARC_V2_ERET]
/Zephyr-latest/drivers/sdhc/
Dsam_hsmci.c269 uint32_t sr; in sam_hsmci_send_cmd() local
287 sr = hsmci->HSMCI_SR; in sam_hsmci_send_cmd()
291 sr &= ~HSMCI_SR_RCRCE; in sam_hsmci_send_cmd()
294 if ((sr & _HSMCI_SR_ERR) != 0) { in sam_hsmci_send_cmd()
295 LOG_DBG("Status register error bits: %08x", sr & _HSMCI_SR_ERR); in sam_hsmci_send_cmd()
298 } while (!(sr & HSMCI_SR_CMDRDY)); in sam_hsmci_send_cmd()
302 sr = hsmci->HSMCI_SR; in sam_hsmci_send_cmd()
303 } while (!((sr & HSMCI_SR_NOTBUSY) && ((sr & HSMCI_SR_DTIP) == 0))); in sam_hsmci_send_cmd()
316 uint32_t sr = 0; in sam_hsmci_wait_write_end() local
321 sr = hsmci->HSMCI_SR; in sam_hsmci_wait_write_end()
[all …]
/Zephyr-latest/include/zephyr/arch/xtensa/
Darch_inlines.h23 #define XTENSA_RSR(sr) \ argument
25 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
34 #define XTENSA_WSR(sr, v) \ argument
36 __asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
/Zephyr-latest/arch/riscv/core/
Disr.S47 RV_E( sr s0, ___callee_saved_t_s0_OFFSET(sp) );\
48 RV_E( sr s1, ___callee_saved_t_s1_OFFSET(sp) );\
49 RV_I( sr s2, ___callee_saved_t_s2_OFFSET(sp) );\
50 RV_I( sr s3, ___callee_saved_t_s3_OFFSET(sp) );\
51 RV_I( sr s4, ___callee_saved_t_s4_OFFSET(sp) );\
52 RV_I( sr s5, ___callee_saved_t_s5_OFFSET(sp) );\
53 RV_I( sr s6, ___callee_saved_t_s6_OFFSET(sp) );\
54 RV_I( sr s7, ___callee_saved_t_s7_OFFSET(sp) );\
55 RV_I( sr s8, ___callee_saved_t_s8_OFFSET(sp) );\
56 RV_I( sr s9, ___callee_saved_t_s9_OFFSET(sp) );\
[all …]
Dreset.S99 sr t1, 0(t0)
101 sr zero, 0(t0)
114 sr t1, 0(t0)
Dswitch.S41 DO_CALLEE_SAVED(sr, a1)
44 sr sp, _thread_offset_to_sp(a1)
47 sr a1, ___thread_t_switch_handle_OFFSET(a1)
Dasm_macros.inc16 .macro sr, rs, mem
27 .macro sr, rs, mem
/Zephyr-latest/drivers/flash/
Dflash_stm32h7x.c62 volatile uint32_t *sr; member
182 uint32_t sr; local
189 sr = regs->ISR;
190 if (sr & (FLASH_FLAG_SNECCERR)) {
197 if (sr & (FLASH_FLAG_DBECCERR)) {
206 if (sr & error_bank) {
211 sr = regs->SR1;
212 if (sr & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1)) {
221 if (sr & error_bank1) {
223 LOG_ERR("Status Bank%d: 0x%08x", 1, sr);
[all …]
/Zephyr-latest/arch/arc/include/
Dswap_macros.h114 sr r13, [_ARC_V2_FPU_STATUS]
116 sr r13, [_ARC_V2_FPU_CTRL]
120 sr r13, [_ARC_V2_FPU_DPFP1L]
122 sr r13, [_ARC_V2_FPU_DPFP1H]
124 sr r13, [_ARC_V2_FPU_DPFP2L]
126 sr r13, [_ARC_V2_FPU_DPFP2H]
135 sr r13, [_ARC_V2_SEC_U_SP]
137 sr r13, [_ARC_V2_SEC_K_SP]
140 sr r13, [_ARC_V2_USER_SP]
142 sr r13, [_ARC_V2_KERNEL_SP]
[all …]
/Zephyr-latest/modules/nrf_wifi/bus/
Dspi_if.c100 uint8_t sr[6]; in spim_read_reg() local
103 .buf = &sr, in spim_read_reg()
104 .len = sizeof(sr), in spim_read_reg()
110 LOG_DBG("err: %d -> %x %x %x %x %x %x", err, sr[0], sr[1], sr[2], sr[3], sr[4], sr[5]); in spim_read_reg()
113 *reg_value = sr[1]; in spim_read_reg()
Dqspi_if.c635 uint8_t sr = -1; in qspi_rdsr() local
637 .buf = &sr, in qspi_rdsr()
638 .len = sizeof(sr), in qspi_rdsr()
646 return (ret < 0) ? ret : sr; in qspi_rdsr()
762 uint8_t sr = (uint8_t)ret; in qspi_nrfx_configure() local
766 bool qe_state = ((sr & qe_mask) != 0U); in qspi_nrfx_configure()
768 LOG_DBG("RDSR %02x QE %d need %d: %s", sr, qe_state, qe_value, in qspi_nrfx_configure()
775 .buf = &sr, in qspi_nrfx_configure()
776 .len = sizeof(sr), in qspi_nrfx_configure()
783 sr ^= qe_mask; in qspi_nrfx_configure()
[all …]
/Zephyr-latest/soc/espressif/esp32/
Desp32-mp.c235 volatile struct cpustart_rec sr; in arch_cpu_start() local
245 sr.cpu = cpu_num; in arch_cpu_start()
246 sr.fn = fn; in arch_cpu_start()
247 sr.stack_top = K_KERNEL_STACK_BUFFER(stack) + sz; in arch_cpu_start()
248 sr.arg = arg; in arch_cpu_start()
249 sr.vecbase = vb; in arch_cpu_start()
250 sr.alive = &alive_flag; in arch_cpu_start()
254 start_rec = &sr; in arch_cpu_start()
/Zephyr-latest/drivers/pwm/
Dpwm_imx.c58 uint32_t cr, sr; in imx_pwm_set_cycles() local
83 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
84 fifoav = PWM_PWMSR_FIFOAV(sr); in imx_pwm_set_cycles()
90 sr = PWM_PWMSR_REG(config->base); in imx_pwm_set_cycles()
91 if (fifoav == PWM_PWMSR_FIFOAV(sr)) { in imx_pwm_set_cycles()
/Zephyr-latest/drivers/can/
Dcan_sja1000.c385 uint8_t sr; in can_sja1000_send() local
410 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_send()
411 if ((sr & CAN_SJA1000_SR_TBS) == 0) { in can_sja1000_send()
412 LOG_ERR("transmit buffer locked, sr = 0x%02x", sr); in can_sja1000_send()
485 uint8_t sr; in can_sja1000_recover() local
496 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_recover()
497 if ((sr & CAN_SJA1000_SR_BS) == 0) { in can_sja1000_recover()
518 while ((sr & CAN_SJA1000_SR_BS) != 0) { in can_sja1000_recover()
524 sr = can_sja1000_read_reg(dev, CAN_SJA1000_SR); in can_sja1000_recover()
574 uint8_t sr; in can_sja1000_handle_receive_irq() local
[all …]
/Zephyr-latest/drivers/usb/device/
Dusb_dc_sam_usbc.c120 static void usb_dc_sam_usbc_isr_sta_dbg(uint32_t ep_idx, uint32_t sr) in usb_dc_sam_usbc_isr_sta_dbg() argument
130 ((sr & USBC_UESTA0_RXSTPI) ? " STP" : "")); in usb_dc_sam_usbc_isr_sta_dbg()
149 #define usb_dc_sam_usbc_isr_sta_dbg(ep_idx, sr) argument
312 uint32_t sr = regs->UESTA[ep_idx]; in usb_dc_ep_isr_sta() local
314 usb_dc_sam_usbc_isr_sta_dbg(ep_idx, sr); in usb_dc_ep_isr_sta()
316 if (sr & USBC_UESTA0_RAMACERI) { in usb_dc_ep_isr_sta()
393 uint32_t sr = regs->UESTA[0]; in usb_dc_ep0_isr() local
401 if (sr & USBC_UESTA0_RXSTPI) { in usb_dc_ep0_isr()
413 if (sr & USBC_UESTA0_RXOUTI) { in usb_dc_ep0_isr()
442 if ((sr & USBC_UESTA0_TXINI) && in usb_dc_ep0_isr()
[all …]
Dusb_dc_sam_usbhs.c172 uint32_t sr = USBHS->USBHS_DEVEPTISR[0] & USBHS->USBHS_DEVEPTIMR[0]; in usb_dc_ep0_isr() local
175 if (sr & USBHS_DEVEPTISR_CTRL_RXSTPI) { in usb_dc_ep0_isr()
180 if (sr & USBHS_DEVEPTISR_RXOUTI) { in usb_dc_ep0_isr()
185 if (sr & USBHS_DEVEPTISR_TXINI) { in usb_dc_ep0_isr()
207 uint32_t sr = USBHS->USBHS_DEVEPTISR[ep_idx] & in usb_dc_ep_isr() local
210 if (sr & USBHS_DEVEPTISR_RXOUTI) { in usb_dc_ep_isr()
220 if (sr & USBHS_DEVEPTISR_TXINI) { in usb_dc_ep_isr()
235 uint32_t sr = USBHS->USBHS_DEVISR & USBHS->USBHS_DEVIMR; in usb_dc_isr() local
238 if (sr & USBHS_DEVISR_EORSM) { in usb_dc_isr()
247 if (sr & USBHS_DEVISR_EORST) { in usb_dc_isr()
[all …]
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h96 sr t0, __soc_esf_t_sp_align_OFFSET(t1)
103 sr t2, __struct_arch_esf_mepc_OFFSET(sp)
115 DO_CALLER_SAVED(sr); \
/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_stm32.c188 uint32_t sr; in ucpd_get_cc() local
210 sr = LL_UCPD_ReadReg(config->ucpd_port, SR); in ucpd_get_cc()
214 vstate_cc1 = (sr & UCPD_SR_TYPEC_VSTATE_CC1_Msk) >> in ucpd_get_cc()
217 vstate_cc2 = (sr & UCPD_SR_TYPEC_VSTATE_CC2_Msk) >> in ucpd_get_cc()
1087 uint32_t sr; in ucpd_isr() local
1140 sr = LL_UCPD_ReadReg(config->ucpd_port, SR); in ucpd_isr()
1143 if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) { in ucpd_isr()
1154 if (sr & tx_done_mask) { in ucpd_isr()
1156 if (sr & UCPD_SR_TXMSGSENT) { in ucpd_isr()
1158 } else if (sr & (UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) { in ucpd_isr()
[all …]
/Zephyr-latest/soc/snps/hsdk4xd/
Dsoc_ctrl.h13 sr r0, [_ARC_V2_LPB_CTRL]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/lll/
Dlll_adv.c64 struct pdu_adv *sr, uint8_t devmatch_ok,
67 struct pdu_adv *sr);
954 struct pdu_adv *sr, uint8_t devmatch_ok, in isr_rx_sr_check() argument
959 ull_filter_lll_rl_addr_allowed(sr->tx_addr, in isr_rx_sr_check()
960 sr->scan_req.scan_addr, in isr_rx_sr_check()
964 isr_rx_sr_adva_check(adv, sr); in isr_rx_sr_check()
968 isr_rx_sr_adva_check(adv, sr); in isr_rx_sr_check()
973 struct pdu_adv *sr) in isr_rx_sr_adva_check() argument
975 return (adv->tx_addr == sr->rx_addr) && in isr_rx_sr_adva_check()
976 !memcmp(adv->adv_ind.addr, sr->scan_req.adv_addr, BDADDR_SIZE); in isr_rx_sr_adva_check()

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