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Searched refs:int_bit_mask (Results 1 – 25 of 30) sorted by relevance

12

/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/native_drivers/
Dppc_rse_drv.c39 dev->data->int_bit_mask = MAIN_PPC0_INT_POS_MASK; in ppc_rse_init()
47 dev->data->int_bit_mask = MAIN_PPCEXP0_INT_POS_MASK; in ppc_rse_init()
53 dev->data->int_bit_mask = MAIN_PPCEXP1_INT_POS_MASK; in ppc_rse_init()
59 dev->data->int_bit_mask = MAIN_PPCEXP2_INT_POS_MASK; in ppc_rse_init()
65 dev->data->int_bit_mask = MAIN_PPCEXP3_INT_POS_MASK; in ppc_rse_init()
73 dev->data->int_bit_mask = PERIPH_PPC0_INT_POS_MASK; in ppc_rse_init()
79 dev->data->int_bit_mask = PERIPH_PPC1_INT_POS_MASK; in ppc_rse_init()
87 dev->data->int_bit_mask = PERIPH_PPCEXP0_INT_POS_MASK; in ppc_rse_init()
93 dev->data->int_bit_mask = PERIPH_PPCEXP1_INT_POS_MASK; in ppc_rse_init()
99 dev->data->int_bit_mask = PERIPH_PPCEXP2_INT_POS_MASK; in ppc_rse_init()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/native_drivers/
Dppc_corstone310_drv.c124 dev->data->int_bit_mask = MAIN_PPC0_INT_POS_MASK; in ppc_corstone310_init()
132 dev->data->int_bit_mask = MAIN_PPCEXP0_INT_POS_MASK; in ppc_corstone310_init()
138 dev->data->int_bit_mask = MAIN_PPCEXP1_INT_POS_MASK; in ppc_corstone310_init()
144 dev->data->int_bit_mask = MAIN_PPCEXP2_INT_POS_MASK; in ppc_corstone310_init()
150 dev->data->int_bit_mask = MAIN_PPCEXP3_INT_POS_MASK; in ppc_corstone310_init()
158 dev->data->int_bit_mask = PERIPH_PPC0_INT_POS_MASK; in ppc_corstone310_init()
164 dev->data->int_bit_mask = PERIPH_PPC1_INT_POS_MASK; in ppc_corstone310_init()
172 dev->data->int_bit_mask = PERIPH_PPCEXP0_INT_POS_MASK; in ppc_corstone310_init()
178 dev->data->int_bit_mask = PERIPH_PPCEXP1_INT_POS_MASK; in ppc_corstone310_init()
184 dev->data->int_bit_mask = PERIPH_PPCEXP2_INT_POS_MASK; in ppc_corstone310_init()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/native_drivers/
Dppc_corstone315_drv.c124 dev->data->int_bit_mask = MAIN_PPC0_INT_POS_MASK; in ppc_corstone315_init()
132 dev->data->int_bit_mask = MAIN_PPCEXP0_INT_POS_MASK; in ppc_corstone315_init()
138 dev->data->int_bit_mask = MAIN_PPCEXP1_INT_POS_MASK; in ppc_corstone315_init()
144 dev->data->int_bit_mask = MAIN_PPCEXP2_INT_POS_MASK; in ppc_corstone315_init()
150 dev->data->int_bit_mask = MAIN_PPCEXP3_INT_POS_MASK; in ppc_corstone315_init()
158 dev->data->int_bit_mask = PERIPH_PPC0_INT_POS_MASK; in ppc_corstone315_init()
164 dev->data->int_bit_mask = PERIPH_PPC1_INT_POS_MASK; in ppc_corstone315_init()
172 dev->data->int_bit_mask = PERIPH_PPCEXP0_INT_POS_MASK; in ppc_corstone315_init()
178 dev->data->int_bit_mask = PERIPH_PPCEXP1_INT_POS_MASK; in ppc_corstone315_init()
184 dev->data->int_bit_mask = PERIPH_PPCEXP2_INT_POS_MASK; in ppc_corstone315_init()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/Native_Driver/
Dppc_sse200_drv.c146 dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; in ppc_sse200_init()
152 dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
158 dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
164 dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
170 dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; in ppc_sse200_init()
176 dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; in ppc_sse200_init()
182 dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; in ppc_sse200_init()
188 dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
194 dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
200 dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
[all …]
Dppc_sse200_drv.h48 uint32_t int_bit_mask; /*!< Interrupt bit mask */ member
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/an524/native_drivers/
Dppc_sse200_drv.c167 dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; in ppc_sse200_init()
173 dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
179 dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
185 dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
191 dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; in ppc_sse200_init()
197 dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; in ppc_sse200_init()
203 dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; in ppc_sse200_init()
209 dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
215 dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
221 dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
[all …]
Dppc_sse200_drv.h50 uint32_t int_bit_mask; /*!< Interrupt bit mask */ member
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Native_Driver/
Dppc_sse200_drv.c146 dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; in ppc_sse200_init()
152 dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
158 dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
164 dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
170 dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; in ppc_sse200_init()
176 dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; in ppc_sse200_init()
182 dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; in ppc_sse200_init()
188 dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
194 dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
200 dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
[all …]
Dppc_sse200_drv.h48 uint32_t int_bit_mask; /*!< Interrupt bit mask */ member
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/native_drivers/
Dppc_sse200_drv.c146 dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; in ppc_sse200_init()
152 dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
158 dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
164 dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
170 dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; in ppc_sse200_init()
176 dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; in ppc_sse200_init()
182 dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; in ppc_sse200_init()
188 dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
194 dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
200 dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
[all …]
Dppc_sse200_drv.h44 uint32_t int_bit_mask; /*!< Interrupt bit mask */ member
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/native_drivers/
Dppc_sse200_drv.c146 dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK; in ppc_sse200_init()
152 dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
158 dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
164 dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
170 dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK; in ppc_sse200_init()
176 dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK; in ppc_sse200_init()
182 dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK; in ppc_sse200_init()
188 dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK; in ppc_sse200_init()
194 dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK; in ppc_sse200_init()
200 dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK; in ppc_sse200_init()
[all …]
Dppc_sse200_drv.h44 uint32_t int_bit_mask; /*!< Interrupt bit mask */ member
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/common/native_drivers/
Dppc_sse300_drv.c242 dev->data->int_bit_mask = MAIN_PPC0_INT_POS_MASK; in ppc_sse300_init()
250 dev->data->int_bit_mask = MAIN_PPCEXP0_INT_POS_MASK; in ppc_sse300_init()
256 dev->data->int_bit_mask = MAIN_PPCEXP1_INT_POS_MASK; in ppc_sse300_init()
262 dev->data->int_bit_mask = MAIN_PPCEXP2_INT_POS_MASK; in ppc_sse300_init()
268 dev->data->int_bit_mask = MAIN_PPCEXP3_INT_POS_MASK; in ppc_sse300_init()
276 dev->data->int_bit_mask = PERIPH_PPC0_INT_POS_MASK; in ppc_sse300_init()
282 dev->data->int_bit_mask = PERIPH_PPC1_INT_POS_MASK; in ppc_sse300_init()
290 dev->data->int_bit_mask = PERIPH_PPCEXP0_INT_POS_MASK; in ppc_sse300_init()
296 dev->data->int_bit_mask = PERIPH_PPCEXP1_INT_POS_MASK; in ppc_sse300_init()
302 dev->data->int_bit_mask = PERIPH_PPCEXP2_INT_POS_MASK; in ppc_sse300_init()
[all …]
/trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/common/native_drivers/
Dppc_alcor_drv.c243 dev->data->int_bit_mask = MAIN_PPC0_INT_POS_MASK; in ppc_alcor_init()
251 dev->data->int_bit_mask = MAIN_PPCEXP0_INT_POS_MASK; in ppc_alcor_init()
257 dev->data->int_bit_mask = MAIN_PPCEXP1_INT_POS_MASK; in ppc_alcor_init()
263 dev->data->int_bit_mask = MAIN_PPCEXP2_INT_POS_MASK; in ppc_alcor_init()
269 dev->data->int_bit_mask = MAIN_PPCEXP3_INT_POS_MASK; in ppc_alcor_init()
277 dev->data->int_bit_mask = PERIPH_PPC0_INT_POS_MASK; in ppc_alcor_init()
283 dev->data->int_bit_mask = PERIPH_PPC1_INT_POS_MASK; in ppc_alcor_init()
291 dev->data->int_bit_mask = PERIPH_PPCEXP0_INT_POS_MASK; in ppc_alcor_init()
297 dev->data->int_bit_mask = PERIPH_PPCEXP1_INT_POS_MASK; in ppc_alcor_init()
303 dev->data->int_bit_mask = PERIPH_PPCEXP2_INT_POS_MASK; in ppc_alcor_init()
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an521/retarget/
Dplatform_retarget_dev.c156 .int_bit_mask = 0,
170 .int_bit_mask = 0,
184 .int_bit_mask = 0,
198 .int_bit_mask = 0,
212 .int_bit_mask = 0,
226 .int_bit_mask = 0,
240 .int_bit_mask = 0,
254 .int_bit_mask = 0,
268 .int_bit_mask = 0,
282 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps2/an519/retarget/
Dplatform_retarget_dev.c156 .int_bit_mask = 0,
170 .int_bit_mask = 0,
184 .int_bit_mask = 0,
198 .int_bit_mask = 0,
212 .int_bit_mask = 0,
226 .int_bit_mask = 0,
240 .int_bit_mask = 0,
254 .int_bit_mask = 0,
268 .int_bit_mask = 0,
282 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Device/Source/
Ddevice_definition.c48 .int_bit_mask = 0,
62 .int_bit_mask = 0,
76 .int_bit_mask = 0,
90 .int_bit_mask = 0,
104 .int_bit_mask = 0,
118 .int_bit_mask = 0,
132 .int_bit_mask = 0,
146 .int_bit_mask = 0,
160 .int_bit_mask = 0,
174 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/common/device/source/
Dplatform_s_device_definition.c56 .int_bit_mask = 0,
70 .int_bit_mask = 0,
84 .int_bit_mask = 0,
98 .int_bit_mask = 0,
112 .int_bit_mask = 0,
126 .int_bit_mask = 0,
140 .int_bit_mask = 0,
154 .int_bit_mask = 0,
168 .int_bit_mask = 0,
182 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/device/source/
Ddevice_definition.c92 .int_bit_mask = 0,
108 .int_bit_mask = 0,
124 .int_bit_mask = 0,
140 .int_bit_mask = 0,
156 .int_bit_mask = 0,
172 .int_bit_mask = 0,
188 .int_bit_mask = 0,
204 .int_bit_mask = 0,
220 .int_bit_mask = 0,
236 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/device/source/
Dplatform_s_device_definition.c52 .int_bit_mask = 0,
66 .int_bit_mask = 0,
80 .int_bit_mask = 0,
94 .int_bit_mask = 0,
108 .int_bit_mask = 0,
122 .int_bit_mask = 0,
136 .int_bit_mask = 0,
150 .int_bit_mask = 0,
164 .int_bit_mask = 0,
178 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/device/source/
Dplatform_s_device_definition.c52 .int_bit_mask = 0,
66 .int_bit_mask = 0,
80 .int_bit_mask = 0,
94 .int_bit_mask = 0,
108 .int_bit_mask = 0,
122 .int_bit_mask = 0,
136 .int_bit_mask = 0,
150 .int_bit_mask = 0,
164 .int_bit_mask = 0,
178 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/common/device/source/
Dplatform_s_device_definition.c55 .int_bit_mask = 0,
69 .int_bit_mask = 0,
83 .int_bit_mask = 0,
97 .int_bit_mask = 0,
111 .int_bit_mask = 0,
125 .int_bit_mask = 0,
139 .int_bit_mask = 0,
153 .int_bit_mask = 0,
167 .int_bit_mask = 0,
181 .int_bit_mask = 0,
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/an524/device/source/
Ddevice_definition.c227 .int_bit_mask = 0,
245 .int_bit_mask = 0,
263 .int_bit_mask = 0,
281 .int_bit_mask = 0,
299 .int_bit_mask = 0,
317 .int_bit_mask = 0,
335 .int_bit_mask = 0,
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/Device/Source/
Ddevice_definition.c48 .int_bit_mask = 0,
62 .int_bit_mask = 0,
76 .int_bit_mask = 0,
90 .int_bit_mask = 0,
104 .int_bit_mask = 0,
118 .int_bit_mask = 0,

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