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Searched refs:NVIC (Results 1 – 25 of 211) sorted by relevance

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/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_manage.c68 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arm_irq_is_enabled()
242 for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) { in irq_target_state_set_all_non_secure()
243 NVIC->ICER[i] = 0xFFFFFFFF; in irq_target_state_set_all_non_secure()
250 for (i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { in irq_target_state_set_all_non_secure()
251 NVIC->ITNS[i] = 0xFFFFFFFF; in irq_target_state_set_all_non_secure()
Dscb.c107 for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) { in z_arm_init_arch_hw_at_boot()
108 NVIC->ICER[i] = 0xFFFFFFFF; in z_arm_init_arch_hw_at_boot()
111 for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) { in z_arm_init_arch_hw_at_boot()
112 NVIC->ICPR[i] = 0xFFFFFFFF; in z_arm_init_arch_hw_at_boot()
/Zephyr-latest/soc/nordic/nrf54h/
Dpm_s2ram.c115 memcpy(backup->ISER, (uint32_t *)NVIC->ISER, sizeof(NVIC->ISER)); in nvic_suspend()
116 memcpy(backup->ISPR, (uint32_t *)NVIC->ISPR, sizeof(NVIC->ISPR)); in nvic_suspend()
117 memcpy(backup->IPR, (uint32_t *)NVIC->IPR, sizeof(NVIC->IPR)); in nvic_suspend()
122 memcpy((uint32_t *)NVIC->ISER, backup->ISER, sizeof(NVIC->ISER)); in nvic_resume()
123 memcpy((uint32_t *)NVIC->ISPR, backup->ISPR, sizeof(NVIC->ISPR)); in nvic_resume()
124 memcpy((uint32_t *)NVIC->IPR, backup->IPR, sizeof(NVIC->IPR)); in nvic_resume()
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc.c43 NVIC->ICER[n] = 0xFFFFFFFFul; in soc_ecia_init()
44 NVIC->ICPR[n] = 0xFFFFFFFFul; in soc_ecia_init()
DKconfig.defconfig.series11 # All NVIC external sources.
/Zephyr-latest/soc/microchip/mec/mec174x/
DKconfig.defconfig.series11 # All NVIC external sources.
/Zephyr-latest/soc/microchip/mec/mec175x/
DKconfig.defconfig.series11 # All NVIC external sources.
/Zephyr-latest/soc/microchip/mec/mech172x/
DKconfig.defconfig.series11 # All NVIC external sources.
/Zephyr-latest/soc/microchip/mec/mec172x/
DKconfig.defconfig.series11 # All NVIC external sources.
/Zephyr-latest/tests/arch/arm/arm_thread_swap/src/
Darm_syscalls.c133 NVIC->STIR = irq_line; in user_thread_entry()
141 NVIC->STIR = irq_line; in user_thread_entry()
/Zephyr-latest/boards/nordic/nrf54l09pdk/doc/
Dindex.rst22 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
52 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/nordic/nrf54l20pdk/doc/
Dindex.rst22 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
53 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/brcm/bcm958401m2/doc/
Dindex.rst27 | NVIC | on-chip | nested vectored interrupt controller |
/Zephyr-latest/boards/norik/octopus_som/doc/
Dindex.rst20 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
53 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/brcm/bcm958402m2/doc/
Dm7.rst27 | NVIC | on-chip | nested vectored interrupt controller |
/Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/
Darm_custom_interrupt.c57 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in z_soc_irq_is_enabled()
/Zephyr-latest/subsys/testsuite/include/zephyr/
Dinterrupt_util.h67 NVIC->STIR = irq; in trigger_irq()
/Zephyr-latest/arch/arm/
DKconfig21 non-GIC or NVIC) interrupt controller.
27 the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
33 N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
35 assumes responsibility for handling the NVIC.
/Zephyr-latest/boards/nordic/nrf51dongle/doc/
Dindex.rst17 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
62 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/actinius/icarus_bee/doc/
Dindex.rst21 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
68 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/actinius/icarus_som/doc/
Dindex.rst21 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
68 | NVIC | on-chip | arch/arm |
/Zephyr-latest/boards/aconno/acn52832/doc/
Dindex.rst15 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
/Zephyr-latest/boards/antmicro/myra_sip_baseboard/support/
Dmyra_sip_baseboard.repl46 nvic0: IRQControllers.NVIC @ {
/Zephyr-latest/tests/arch/arm/arm_irq_vector_table/src/
Darm_irq_vector_table.c118 NVIC->STIR = _ISR_OFFSET + ii; in ZTEST()
/Zephyr-latest/boards/nordic/nrf51dk/doc/
Dindex.rst17 * :abbr:`NVIC (Nested Vectored Interrupt Controller)`
62 | NVIC | on-chip | arch/arm |

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