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Searched refs:NVIC (Results 1 – 25 of 31) sorted by relevance

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/trusted-firmware-m-3.5.0/platform/ext/target/nuvoton/m2354/
Dtarget_cfg.c232 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
233 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
339 if(SCU_INIT_PNSSET0_VAL & BIT9) NVIC->ITNS[1] |= BIT22; /* Int of USBH_INT */ in mpc_init_cfg()
340 if(SCU_INIT_PNSSET0_VAL & BIT13) NVIC->ITNS[2] |= BIT0; /* Int of SDHOST0_INT */ in mpc_init_cfg()
341 if(SCU_INIT_PNSSET0_VAL & BIT24) NVIC->ITNS[3] |= BIT2; /* Int of PDMA1_INT */ in mpc_init_cfg()
342 if(SCU_INIT_PNSSET1_VAL & BIT18) NVIC->ITNS[2] |= BIT7; /* Int of CRYPTO */ in mpc_init_cfg()
343 if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT15; /* Int of EWDT_INT */ in mpc_init_cfg()
344 if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT16; /* Int of EWWDT_INT */ in mpc_init_cfg()
345 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT10; /* Int of EADC0_INT */ in mpc_init_cfg()
346 if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT11; /* Int of EADC1_INT */ in mpc_init_cfg()
[all …]
/trusted-firmware-m-3.5.0/platform/ext/target/arm/musca_b1/
Dtfm_hal_platform.c58 NVIC->ICPR[0] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
59 NVIC->ICPR[1] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
60 NVIC->ICPR[2] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
61 NVIC->ICPR[3] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
62 NVIC->ICPR[4] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
63 NVIC->ICPR[5] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
64 NVIC->ICPR[6] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
65 NVIC->ICPR[7] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_hal_system_reset()
Dtarget_cfg.c260 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
261 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/musca_s1/services/src/
Dtfm_platform_system.c22 NVIC->ICPR[0] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
23 NVIC->ICPR[1] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
24 NVIC->ICPR[2] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
25 NVIC->ICPR[3] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
26 NVIC->ICPR[4] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
27 NVIC->ICPR[5] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
28 NVIC->ICPR[6] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
29 NVIC->ICPR[7] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/musca_b1/services/src/
Dtfm_platform_system.c21 NVIC->ICPR[0] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
22 NVIC->ICPR[1] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
23 NVIC->ICPR[2] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
24 NVIC->ICPR[3] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
25 NVIC->ICPR[4] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
26 NVIC->ICPR[5] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
27 NVIC->ICPR[6] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
28 NVIC->ICPR[7] = UINT32_MAX; /* Clear all pending interrupts */ in tfm_platform_hal_system_reset()
/trusted-firmware-m-3.5.0/platform/ext/target/nordic_nrf/common/core/
Dhw_init.c112 for (int i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) { in hw_init_reset_on_boot()
113 NVIC->ICER[i] = 0xFFFFFFFF; in hw_init_reset_on_boot()
116 for (int i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) { in hw_init_reset_on_boot()
117 NVIC->ICPR[i] = 0xFFFFFFFF; in hw_init_reset_on_boot()
/trusted-firmware-m-3.5.0/platform/ext/target/nuvoton/m2351/partition/
Dpartition_M2351.h798 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; in TZ_SAU_Setup()
802 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; in TZ_SAU_Setup()
806 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; in TZ_SAU_Setup()
810 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; in TZ_SAU_Setup()
/trusted-firmware-m-3.5.0/platform/ext/cmsis/
Dcore_cm0plus.h655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
746 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
764 … return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); in __NVIC_GetEnableIRQ()
783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
802 … return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); in __NVIC_GetPendingIRQ()
821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
836 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
854 … NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
879 …return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
Dcore_cm23.h1389 …#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration str… macro
1529 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
1547 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
1566 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
1585 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
1604 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
1619 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
1636 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
1658 …return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in NVIC_GetTargetState()
1679 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); in NVIC_SetTargetState()
[all …]
Dcore_cm4.h1562 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc… macro
1689 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
1707 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
1726 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
1745 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
1764 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
1779 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
1796 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
1818 …NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint… in __NVIC_SetPriority()
1841 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()
Dcore_cm33.h2213 …#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration str… macro
2395 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
2413 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
2432 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
2451 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
2470 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
2485 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
2502 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
2524 …return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in NVIC_GetTargetState()
2545 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); in NVIC_SetTargetState()
[all …]
Dcore_armv81mml.h3108 …#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration str… macro
3295 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
3313 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
3332 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
3351 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
3370 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
3385 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
3402 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
3424 …return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in NVIC_GetTargetState()
3445 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); in NVIC_SetTargetState()
[all …]
Dcore_cm55.h3610 …#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration str… macro
3857 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
3875 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
3894 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
3913 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
3932 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
3947 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
3964 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
3986 …return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in NVIC_GetTargetState()
4007 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); in NVIC_SetTargetState()
[all …]
Dcore_cm85.h3514 …#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration str… macro
3706 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
3724 …return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetEnableIRQ()
3743 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
3762 …return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetPendingIRQ()
3781 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
3796 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
3813 …return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in __NVIC_GetActive()
3835 …return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) … in NVIC_GetTargetState()
3856 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); in NVIC_SetTargetState()
[all …]
/trusted-firmware-m-3.5.0/platform/ext/target/nuvoton/m2351/
Dtarget_cfg.c154 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
155 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/stm/common/stm32l5xx/secure/
Dtarget_cfg.c78 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) in nvic_interrupt_target_state_cfg()
80 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/mps2/an519/
Dtarget_cfg.c188 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
189 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/nordic_nrf/common/nrf91/
Dtarget_cfg.c474 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
475 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/mps3/an547/
Dtarget_cfg.c140 for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) { in nvic_interrupt_target_state_cfg()
141 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/mps3/an552/
Dtarget_cfg.c140 for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) { in nvic_interrupt_target_state_cfg()
141 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/nxp/lpcxpresso55s69/
Dtarget_cfg.c134 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
135 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/rss/common/
Dtarget_cfg.c203 for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) { in nvic_interrupt_target_state_cfg()
204 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/lairdconnectivity/common/bl5340/
Dtarget_cfg.c593 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
594 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/nordic_nrf/common/nrf5340/
Dtarget_cfg.c601 for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
602 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()
/trusted-firmware-m-3.5.0/platform/ext/target/arm/musca_s1/
Dtarget_cfg.c267 for (uint8_t i=0; i<sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]); i++) { in nvic_interrupt_target_state_cfg()
268 NVIC->ITNS[i] = 0xFFFFFFFF; in nvic_interrupt_target_state_cfg()

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