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/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/libraries/
Ddma350_lib_unprivileged.h37 enum dma350_lib_error_t dma350_clear_done_irq_unpriv(uint8_t channel);
52 enum dma350_lib_error_t dma350_memcpy_unpriv(uint8_t channel, const void* src,
70 enum dma350_lib_error_t dma350_memmove_unpriv(uint8_t channel, const void* src,
102 enum dma350_lib_error_t dma350_draw_from_canvas_unpriv(uint8_t channel,
137 enum dma350_lib_error_t dma350_draw_from_bitmap_unpriv(uint8_t channel,
166 enum dma350_lib_error_t dma350_2d_copy_unpriv(uint8_t channel,
183 enum dma350_lib_error_t dma350_ch_get_status_unpriv(uint8_t channel,
187 enum dma350_lib_error_t dma350_draw_from_bitmap_unpriv(uint8_t channel, in dma350_draw_from_bitmap_unpriv() argument
196 return dma350_draw_from_canvas_unpriv(channel, src, des, in dma350_draw_from_bitmap_unpriv()
203 enum dma350_lib_error_t dma350_2d_copy_unpriv(uint8_t channel, in dma350_2d_copy_unpriv() argument
[all …]
Ddma350_lib_unprivileged.c15 enum dma350_lib_error_t dma350_memcpy_unpriv(uint8_t channel, const void* src, in dma350_memcpy_unpriv() argument
27 ret_val = request_dma350_priv_config(DMA_CALL_MEMCPY, channel, in dma350_memcpy_unpriv()
33 enum dma350_lib_error_t dma350_memmove_unpriv(uint8_t channel, const void* src, in dma350_memmove_unpriv() argument
45 ret_val = request_dma350_priv_config(DMA_CALL_MEMMOVE, channel, in dma350_memmove_unpriv()
51 enum dma350_lib_error_t dma350_draw_from_canvas_unpriv(uint8_t channel, in dma350_draw_from_canvas_unpriv() argument
76 ret_val = request_dma350_priv_config(DMA_CALL_DRAW_FROM_CANVAS, channel, in dma350_draw_from_canvas_unpriv()
82 enum dma350_lib_error_t dma350_clear_done_irq_unpriv(uint8_t channel) in dma350_clear_done_irq_unpriv() argument
86 ret_val = request_dma350_priv_config(DMA_CLEAR_DONE_IRQ, channel, NULL); in dma350_clear_done_irq_unpriv()
91 enum dma350_lib_error_t dma350_ch_get_status_unpriv(uint8_t channel, in dma350_ch_get_status_unpriv() argument
96 ret_val = request_dma350_priv_config(DMA_GET_STATUS, channel, status); in dma350_ch_get_status_unpriv()
Ddma350_checker_layer.c57 static enum dma350_lib_error_t dma350_get_channel(uint8_t channel, struct dma350_ch_dev_t** ch_dev) in dma350_get_channel() argument
59 if(channel >= DMA350_CHECKER_CHANNELS.number_of_channels) { in dma350_get_channel()
62 *ch_dev = DMA350_CHECKER_CHANNELS.channels[channel]; in dma350_get_channel()
157 …dma350_for_unprivileged_actor(enum dma350_config_type_t config_type, uint8_t channel, void* config) in config_dma350_for_unprivileged_actor() argument
162 ret_val = dma350_get_channel(channel, &ch_dev); in config_dma350_for_unprivileged_actor()
Ddma350_privileged_config.h31 enum dma350_config_type_t config_type, uint8_t channel, void *config);
Ddma350_checker_layer.h88 …ma350_for_unprivileged_actor(enum dma350_config_type_t config_type, uint8_t channel, void* config);
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/native_drivers/
Dmhu_v2_x.h117 uint32_t channel, uint32_t val);
134 uint32_t channel, uint32_t *value);
150 uint32_t channel);
167 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value);
184 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
201 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
217 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
233 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
249 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
400 const struct mhu_v2_x_dev_t *dev, uint32_t *channel);
Ddma350_drv.c93 uint8_t channel) in dma350_set_ch_secure() argument
100 dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & ~(0x1UL << channel); in dma350_set_ch_secure()
101 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_secure()
109 uint8_t channel) in dma350_set_ch_nonsecure() argument
116 dev->cfg->dma_sec_cfg->SCFG_CHSEC0 | (0x1UL << channel); in dma350_set_ch_nonsecure()
117 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_nonsecure()
125 uint8_t channel) in dma350_set_ch_privileged() argument
130 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_privileged()
132 dev->cfg->dma_nsec_ctrl->NSEC_CHPTR = channel; in dma350_set_ch_privileged()
142 dev->cfg->dma_sec_ctrl->SEC_CHPTR = channel; in dma350_set_ch_privileged()
[all …]
Dmhu_v2_x.c207 uint32_t channel, uint32_t val) in mhu_v2_x_channel_send() argument
216 (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; in mhu_v2_x_channel_send()
224 uint32_t channel, uint32_t *value) in mhu_v2_x_channel_poll() argument
233 *value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st; in mhu_v2_x_channel_poll()
241 uint32_t channel) in mhu_v2_x_channel_clear() argument
250 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; in mhu_v2_x_channel_clear()
258 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value) in mhu_v2_x_channel_receive() argument
267 *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; in mhu_v2_x_channel_receive()
275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set() argument
284 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; in mhu_v2_x_channel_mask_set()
[all …]
Ddma350_drv.h254 uint8_t channel);
268 uint8_t channel);
289 uint8_t channel);
303 uint8_t channel);
Ddma350_ch_drv.h105 const uint8_t channel; /*!< DMA350 DMA Channel number */ member
/trusted-firmware-m-3.4.0/platform/ext/target/arm/corstone1000/Native_Driver/
Dmhu_v2_x.h117 uint32_t channel, uint32_t val);
134 uint32_t channel, uint32_t *value);
150 uint32_t channel);
167 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value);
184 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
201 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
217 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
233 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
249 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
400 const struct mhu_v2_x_dev_t *dev, uint32_t *channel);
Dmhu_v2_x.c207 uint32_t channel, uint32_t val) in mhu_v2_x_channel_send() argument
216 (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; in mhu_v2_x_channel_send()
224 uint32_t channel, uint32_t *value) in mhu_v2_x_channel_poll() argument
233 *value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st; in mhu_v2_x_channel_poll()
241 uint32_t channel) in mhu_v2_x_channel_clear() argument
250 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; in mhu_v2_x_channel_clear()
258 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value) in mhu_v2_x_channel_receive() argument
267 *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; in mhu_v2_x_channel_receive()
275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set() argument
284 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; in mhu_v2_x_channel_mask_set()
[all …]
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/Native_Driver/
Dmhu_v2_x.h119 uint32_t channel, uint32_t val);
135 uint32_t channel);
152 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value);
169 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
186 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
202 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
218 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
234 const struct mhu_v2_x_dev_t *dev, uint32_t channel);
385 const struct mhu_v2_x_dev_t *dev, uint32_t *channel);
Dmhu_v2_x.c207 uint32_t channel, uint32_t val) in mhu_v2_x_channel_send() argument
216 (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; in mhu_v2_x_channel_send()
224 uint32_t channel) in mhu_v2_x_channel_clear() argument
233 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; in mhu_v2_x_channel_clear()
241 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value) in mhu_v2_x_channel_receive() argument
250 *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; in mhu_v2_x_channel_receive()
258 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set() argument
267 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; in mhu_v2_x_channel_mask_set()
275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_clear() argument
284 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_clr = mask; in mhu_v2_x_channel_mask_clear()
[all …]
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/fvp/native_drivers/
Ddma350_drv.c93 uint8_t channel) in dma350_set_ch_secure() argument
100 dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & ~(0x1UL << channel); in dma350_set_ch_secure()
101 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_secure()
109 uint8_t channel) in dma350_set_ch_nonsecure() argument
116 dev->cfg->dma_sec_cfg->SCFG_CHSEC0 | (0x1UL << channel); in dma350_set_ch_nonsecure()
117 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_nonsecure()
125 uint8_t channel) in dma350_set_ch_privileged() argument
130 if (dev->cfg->dma_sec_cfg->SCFG_CHSEC0 & (0x1UL << channel)) { in dma350_set_ch_privileged()
132 dev->cfg->dma_nsec_ctrl->NSEC_CHPTR = channel; in dma350_set_ch_privileged()
142 dev->cfg->dma_sec_ctrl->SEC_CHPTR = channel; in dma350_set_ch_privileged()
[all …]
Ddma350_drv.h254 uint8_t channel);
268 uint8_t channel);
289 uint8_t channel);
303 uint8_t channel);
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/fvp/libraries/
Ddma350_checker_layer.c57 static enum dma350_lib_error_t dma350_get_channel(uint8_t channel, struct dma350_ch_dev_t** ch_dev) in dma350_get_channel() argument
59 if(channel >= DMA350_CHECKER_CHANNELS.number_of_channels) { in dma350_get_channel()
62 *ch_dev = DMA350_CHECKER_CHANNELS.channels[channel]; in dma350_get_channel()
157 …dma350_for_unprivileged_actor(enum dma350_config_type_t config_type, uint8_t channel, void* config) in config_dma350_for_unprivileged_actor() argument
162 ret_val = dma350_get_channel(channel, &ch_dev); in config_dma350_for_unprivileged_actor()
Ddma350_privileged_config.h31 enum dma350_config_type_t config_type, uint8_t channel, void *config);
Ddma350_checker_layer.h88 …ma350_for_unprivileged_actor(enum dma350_config_type_t config_type, uint8_t channel, void* config);
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/
Ddma350_privileged_config.c17 uint8_t channel, void* config) in request_dma350_priv_config() argument
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/device/source/
Ddevice_definition.c528 .channel = 0},
536 .channel = 1},
544 .channel = 2},
552 .channel = 3},
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/device/source/
Dplatform_s_device_definition.c412 .channel = 0},
417 .channel = 1},
/trusted-firmware-m-3.4.0/platform/ext/target/nxp/common/Native_Driver/components/uart/
Dfsl_adapter_usart.c881 DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel); in HAL_UartDMADeinit()
885 DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel); in HAL_UartDMADeinit()
/trusted-firmware-m-3.4.0/docs/technical_references/design_docs/
Dtfm_secure_partition_runtime_library.rst68 on input to avoid execution timing side channel attack.
/trusted-firmware-m-3.4.0/docs/technical_references/design_docs/dual-cpu/
Dmailbox_design_on_dual_core_system.rst246 channel to each notification routine respectively, to implement a *full-duplex*
249 channel, proper synchronization should be implemented to prevent conflicts

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