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Searched refs:TFM_TIMER0_IRQ (Results 1 – 25 of 29) sorted by relevance

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/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an547/
Dtfm_interrupts.c33 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
34 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
35 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h25 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an552/
Dtfm_interrupts.c35 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
36 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
37 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h25 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_s1/
Dtfm_interrupts.c33 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
34 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
35 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/
Dtfm_interrupts.c33 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
34 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
35 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an519/
Dtfm_interrupts.c34 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
35 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
36 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an524/
Dtfm_interrupts.c33 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
34 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
35 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an521/
Dtfm_interrupts.c33 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
34 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
35 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/
Dtfm_interrupts.c45 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
46 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
47 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h25 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/
Dtfm_interrupts.c35 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
36 NVIC_ClearTargetState(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
37 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h25 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/cypress/psoc64/
Dtfm_interrupts.c36 NVIC_SetPriority(TFM_TIMER0_IRQ, DEFAULT_IRQ_PRIORITY); in tfm_timer0_irq_init()
37 NVIC_DisableIRQ(TFM_TIMER0_IRQ); in tfm_timer0_irq_init()
Dtfm_peripherals_def.h24 #define TFM_TIMER0_IRQ (NvicMux3_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/common/
Dtfm_peripherals_def.h18 #define TFM_TIMER0_IRQ (TMR0_IRQn) macro
/trusted-firmware-m-3.4.0/platform/ext/target/nxp/lpcxpresso55s69/
Dtfm_peripherals_def.h19 #define TFM_TIMER0_IRQ CTIMER2_IRQn /* (tfm_core_irq_signal_data_t->irq_lin… macro
/trusted-firmware-m-3.4.0/platform/ext/target/cypress/psoc64/Device/Source/
Ddevice_definition.c101 .intrSrc = TFM_TIMER0_IRQ, /* NVIC #3 */
/trusted-firmware-m-3.4.0/platform/ext/target/nordic_nrf/common/nrf91/
Dtfm_peripherals_def.h48 #define TFM_TIMER0_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER0)) macro
/trusted-firmware-m-3.4.0/platform/ext/target/lairdconnectivity/common/bl5340/
Dtfm_peripherals_def.h51 #define TFM_TIMER0_IRQ (TIMER0_IRQn) macro

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