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/trusted-firmware-a-latest/plat/imx/common/
Dimx_sip_svc.c22 u_register_t x3, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
37 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
40 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
44 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
46 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
51 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
53 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
56 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
[all …]
Dimx_sip_handler.c42 u_register_t x3, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
73 u_register_t x3) in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
96 u_register_t x3) in imx_wakeup_src_handler() argument
141 u_register_t x3, in imx_misc_set_temp_handler() argument
144 return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4); in imx_misc_set_temp_handler()
153 u_register_t x3, in imx_src_handler() argument
181 u_register_t x3, in imx_get_commit_hash() argument
207 u_register_t x3, in imx_buildinfo_handler() argument
[all …]
/trusted-firmware-a-latest/plat/hisilicon/hikey/
Dhisi_pwrc_sram.S29 mrs x3, actlr_el3
30 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
31 msr actlr_el3, x3
33 mrs x3, actlr_el2
34 orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT
35 msr actlr_el2, x3
37 ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
42 pen: ldr x4, [x3, x0, LSL #3]
48 mov x3, #0x0
/trusted-firmware-a-latest/lib/libc/aarch64/
Dmemset.S22 mov x3, x0 /* keep x0 */
28 strb w1, [x3], #1
31 tst x3, #7
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
57 str w1, [x3], #4 /* write 4 bytes */
59 strh w1, [x3], #2 /* write 2 bytes */
[all …]
/trusted-firmware-a-latest/plat/imx/common/include/
Dimx_sip_svc.h53 u_register_t x2, u_register_t x3,
57 u_register_t x2, u_register_t x3);
59 u_register_t x2, u_register_t x3);
61 u_register_t x1, u_register_t x2, u_register_t x3);
65 u_register_t x1, u_register_t x2, u_register_t x3);
68 u_register_t x2, u_register_t x3);
73 u_register_t x2, u_register_t x3, void *handle);
78 u_register_t x2, u_register_t x3, u_register_t x4);
83 u_register_t x2, u_register_t x3);
85 u_register_t x2, u_register_t x3, u_register_t x4);
[all …]
/trusted-firmware-a-latest/plat/arm/board/tc/include/
Dtc_helpers.S36 lsl x3, x0, #MPIDR_AFFINITY_BITS
37 csel x3, x3, x0, eq
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/aarch64/
Dls1028a.S151 mov x3, x30
163 mov x30, x3
176 mov x3, x30
197 mov x30, x3
366 mrs x3, osdlr_el1
367 orr x3, x3, #OSDLR_EL1_DLK_LOCK
368 msr osdlr_el1, x3
372 mov x3, #ICC_IGRPEN0_EL1_EN
373 msr ICC_IGRPEN0_EL1, x3
386 ldr x3, =NXP_TIMER_ADDR
[all …]
/trusted-firmware-a-latest/services/std_svc/
Dstd_svc_setup.c99 u_register_t x3, in std_svc_smc_handler() argument
110 x3 &= UINT32_MAX; in std_svc_smc_handler()
133 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
151 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
162 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
169 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
176 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
183 return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
191 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
196 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
[all …]
Dpci_svc.c44 u_register_t x3, in pci_smc_handler() argument
73 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
79 if (pci_read_config(x1, x2, x3, &ret) != 0U) { in pci_smc_handler()
89 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
92 ret = pci_write_config(x1, x2, x3, x4); in pci_smc_handler()
101 if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) { in pci_smc_handler()
/trusted-firmware-a-latest/plat/nxp/common/aarch64/
Dbl31_data.S161 clz x3, x0
163 sub x0, x0, x3
173 ldr x3, =BC_PSCI_BASE
174 add x3, x3, x1
184 mov x3, #SEC_REGION_SIZE
185 mul x3, x3, x0
192 sub x1, x3, x1
197 ldr x3, =SECONDARY_TOP
200 sub x3, x3, x1
206 str x2, [x3]
[all …]
/trusted-firmware-a-latest/lib/pmf/
Dpmf_smc.c20 u_register_t x3, in pmf_smc_handler() argument
37 x3 = (uint32_t)x3; in pmf_smc_handler()
47 (unsigned int)x3, &ts_value); in pmf_smc_handler()
60 (unsigned int)x3, &ts_value); in pmf_smc_handler()
/trusted-firmware-a-latest/plat/arm/board/arm_fpga/aarch64/
Dfpga_helpers.S80 ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
81 cmp x3, #PLAT_FPGA_HOLD_STATE_GO
86 ldr x3, [x2]
87 br x3
136 lsl x3, x0, #MPIDR_AFFINITY_BITS
137 csel x3, x3, x0, eq
140 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
141 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a-latest/plat/mediatek/common/
Dmtk_sip_svc.c28 u_register_t x3, in mediatek_plat_sip_handler() argument
43 u_register_t x3, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
94 u_register_t x3, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/trusted-firmware-a-latest/lib/aarch64/
Dcache_helpers.S26 dcache_line_size x2, x3
28 sub x3, x2, #1
29 bic x0, x0, x3
42 mov x3, x30
45 mov x30, x3
99 dcache_line_size x2, x3
100 sub x3, x2, #1
101 bic x0, x0, x3
131 ubfx x3, x9, \shift, \fw
132 lsl x3, x3, \ls
[all …]
Dmisc_helpers.S157 block_size .req x3 /* Size of a block in bytes as read in DCZID_EL0 */
392 orr x3, x0, x1
393 tst x3, #0xf
400 ldp x3, x4, [x1], #16
401 stp x3, x4, [x0], #16
529 1: ldr x3, [x1]
532 cmp x3, x6
536 cmp x3, x7
538 add x3, x3, x0
539 str x3, [x1]
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/aarch64/
Dls1088a.S173 mov x3, x30
184 mov x30, x3
216 mov x3, x30
241 mov x30, x3
409 mrs x3, osdlr_el1
410 orr x3, x3, #OSDLR_EL1_DLK_LOCK
411 msr osdlr_el1, x3
415 mov x3, #ICC_IGRPEN0_EL1_EN
416 msr ICC_IGRPEN0_EL1, x3
429 ldr x3, =NXP_TIMER_ADDR
[all …]
/trusted-firmware-a-latest/plat/arm/common/
Darm_sip_svc.c54 u_register_t x3, in arm_sip_handler() argument
69 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
78 return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
87 return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
105 (uint32_t) x1, (uint32_t) x2, (uint32_t) x3, in arm_sip_handler()
144 return plat_arm_sip_handler(smc_fid, x1, x2, x3, x4, in arm_sip_handler()
/trusted-firmware-a-latest/plat/mediatek/mt8195/
Dplat_sip_calls.c21 u_register_t x3, in mediatek_plat_sip_handler() argument
33 ret = emi_mpu_sip_handler(x1, x2, x3); in mediatek_plat_sip_handler()
43 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); in mediatek_plat_sip_handler()
48 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
53 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); in mediatek_plat_sip_handler()
/trusted-firmware-a-latest/plat/mediatek/mt8186/
Dplat_sip_calls.c19 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
40 ret = msdc_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/trusted-firmware-a-latest/plat/mediatek/mt8192/
Dplat_sip_calls.c18 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/trusted-firmware-a-latest/plat/intel/soc/common/
Dsocfpga_sip_svc.c43 uint64_t x3, in socfpga_sip_handler() argument
708 u_register_t x3, argument
783 (uint32_t)x3, &retval);
845 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
856 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
868 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
870 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
882 if (x3 == FCS_MODE_DECRYPT) {
885 } else if (x3 == FCS_MODE_ENCRYPT) {
900 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
[all …]
/trusted-firmware-a-latest/services/std_svc/rmmd/trp/
Dtrp_main.c30 uint64_t x3) in trp_setup() argument
49 if ((void *)x3 == NULL) { in trp_setup()
58 trp_shared_region_start = x3; in trp_setup()
69 uint64_t x2, uint64_t x3) in trp_validate_warmboot_args() argument
83 return ((x1 | x2 | x3) == 0UL) ? 0 : E_RMM_BOOT_UNKNOWN; in trp_validate_warmboot_args()
160 unsigned long long x3, unsigned long long x4, in trp_rmi_handler() argument
166 (void)x3; in trp_rmi_handler()
/trusted-firmware-a-latest/plat/arm/board/fvp/aarch64/
Dfvp_helpers.S163 lsl x3, x0, #MPIDR_AFFINITY_BITS
164 csel x3, x3, x0, eq
167 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
168 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
169 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/
Dplat_trampoline.S49 ldp x3, x4, [x1], #16
50 stp x3, x4, [x0], #16
135 mov x3, #MC_SECURITY_CFG3_0
136 ldr w1, [x0, x3]
138 mov x3, #MC_SECURITY_CFG0_0
139 ldr w2, [x0, x3]
140 orr x3, x1, x2 /* TZDRAM base */
147 str x0, [x3, x2] /* set value in TZDRAM */
/trusted-firmware-a-latest/plat/xilinx/zynqmp/
Dsip_svc_setup.c76 u_register_t x3, in sip_svc_smc_handler() argument
83 smc_fid, x1, x2, x3, x4); in sip_svc_smc_handler()
92 return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in sip_svc_smc_handler()
98 return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in sip_svc_smc_handler()
115 return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in sip_svc_smc_handler()

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