43 				   uint64_t x3,  in socfpga_sip_handler()  argument
708 			 u_register_t x3,  argument
783 						 (uint32_t)x3, &retval);
845 		status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
856 		status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
868 			status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
870 			status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
882 		if (x3 == FCS_MODE_DECRYPT) {
885 		} else if (x3 == FCS_MODE_ENCRYPT) {
900 		status = intel_fcs_random_number_gen_ext(x1, x2, x3,
913 		status = intel_fcs_cntr_set_preauth(x1, x2, x3,
938 		status = intel_fcs_attestation_subkey(x1, x2, x3,
940 		SMC_RET4(handle, status, mbox_error, x3, x4);
943 		status = intel_fcs_get_measurement(x1, x2, x3,
945 		SMC_RET4(handle, status, mbox_error, x3, x4);
949 					(uint32_t *) &x3, &mbox_error);
950 		SMC_RET4(handle, status, mbox_error, x2, x3);
969 		status = intel_fcs_export_crypto_service_key(x1, x2, x3,
971 		SMC_RET4(handle, status, mbox_error, x3, x4);
979 		status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
981 		SMC_RET4(handle, status, mbox_error, x3, x4);
985 		status = intel_fcs_get_digest_init(x1, x2, x3,
992 		status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1000 		status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1008 		status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1016 		status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1023 		status = intel_fcs_mac_verify_init(x1, x2, x3,
1031 		status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1040 		status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1049 		status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1058 		status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1065 		status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1073 					x3, x4, x5, (uint32_t *) &x6, false,
1081 					x3, x4, x5, (uint32_t *) &x6, true,
1089 					x2, x3, x4, x5, (uint32_t *) &x6, false,
1097 					x2, x3, x4, x5, (uint32_t *) &x6, true,
1103 		status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1110 		status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1116 		status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1123 		status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1129 		status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1138 					x1, x2, x3, x4, x5, (uint32_t *) &x6,
1147 					x1, x2, x3, x4, x5, (uint32_t *) &x6,
1156 					x1, x2, x3, x4, x5, (uint32_t *) &x6,
1165 					x1, x2, x3, x4, x5, (uint32_t *) &x6,
1171 		status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1176 		status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1178 		SMC_RET4(handle, status, mbox_error, x3, x4);
1182 		status = intel_fcs_ecdh_request_init(x1, x2, x3,
1189 		status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1195 		status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1202 		status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1209 		status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1233 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1241 			 u_register_t x3,  argument
1251 		return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1254 		return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,