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/trusted-firmware-a-latest/lib/compiler-rt/builtins/
Dpopcountdi2.c18 du_int x2 = (du_int)a; in __popcountdi2() local
19 x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); in __popcountdi2()
21 x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); in __popcountdi2()
23 x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; in __popcountdi2()
25 su_int x = (su_int)(x2 + (x2 >> 32)); in __popcountdi2()
/trusted-firmware-a-latest/plat/nxp/common/aarch64/
Dbl31_data.S37 clz x2, x0
39 sub x0, x0, x2
48 ldr x2, =BC_PSCI_BASE
49 add x2, x2, x1
58 mov x2, #SEC_REGION_SIZE
59 mul x2, x2, x0
65 sub x1, x2, x1
70 ldr x2, =SECONDARY_TOP
73 sub x2, x2, x1
77 dc ivac, x2
[all …]
/trusted-firmware-a-latest/plat/imx/common/
Dimx_sip_svc.c21 u_register_t x2, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
37 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
40 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
44 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
46 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
51 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
53 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
56 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
[all …]
Dimx_sip_handler.c41 u_register_t x2, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
72 u_register_t x2, in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
95 u_register_t x2, in imx_wakeup_src_handler() argument
115 u_register_t x2) in imx_otp_handler() argument
126 ret = sc_misc_otp_fuse_write(ipc_handle, x1, x2); in imx_otp_handler()
140 u_register_t x2, in imx_misc_set_temp_handler() argument
144 return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4); in imx_misc_set_temp_handler()
152 u_register_t x2, in imx_src_handler() argument
[all …]
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/
Dplat_trampoline.S25 mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26 lsl x2, x2, #16
27 add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28 cmp x1, x2
34 mov x2, #TEGRA194_STATE_SYSTEM_RESUME
35 add x1, x1, x2
42 adr x2, __tegra194_cpu_reset_handler_data
43 ldr x2, [x2, #8]
47 cmp x2, #16
51 sub x2, x2, #16
[all …]
/trusted-firmware-a-latest/lib/romlib/
Dinit.s21 adrp x2, __DATA_RAM_END__
22 add x2, x2, :lo12:__DATA_RAM_END__
23 sub x2, x2, x0
29 adrp x2, __BSS_END__
30 add x2, x2, :lo12:__BSS_END__
31 sub x2, x2, x0
/trusted-firmware-a-latest/lib/extensions/amu/aarch64/
Damu_helpers.S61 adr x2, 1f
74 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
76 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
78 br x2
137 adr x2, 1f
150 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
152 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
154 br x2
181 adr x2, 1f
198 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
[all …]
/trusted-firmware-a-latest/plat/imx/common/include/
Dimx_sip_svc.h53 u_register_t x2, u_register_t x3,
57 u_register_t x2, u_register_t x3);
59 u_register_t x2, u_register_t x3);
61 u_register_t x1, u_register_t x2, u_register_t x3);
65 u_register_t x1, u_register_t x2, u_register_t x3);
68 u_register_t x2, u_register_t x3);
73 u_register_t x2, u_register_t x3, void *handle);
78 u_register_t x2, u_register_t x3, u_register_t x4);
83 u_register_t x2, u_register_t x3);
85 u_register_t x2, u_register_t x3, u_register_t x4);
[all …]
/trusted-firmware-a-latest/plat/st/stm32mp1/services/
Dbsec_svc.c17 uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3, in bsec_main() argument
25 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
29 result = bsec_program_otp(x3, x2); in bsec_main()
33 result = bsec_write_otp(x3, x2); in bsec_main()
37 result = bsec_read_otp(&tmp_data, x2); in bsec_main()
42 result = bsec_shadow_register(x2); in bsec_main()
47 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
52 result = bsec_write_otp(tmp_data, x2); in bsec_main()
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/aarch64/
Dls1088a.S151 mov x2, x0
158 tst x0, x2
196 ldr x2, =NXP_DCFG_ADDR
200 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
204 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
306 mov x2, #1
307 lsl x2, x2, x1
311 orr x2, x2, x1
313 orr x2, x2, #ICC_SGI0R_EL1_INTID
315 msr ICC_SGI0R_EL1, x2
[all …]
/trusted-firmware-a-latest/lib/cpus/aarch64/
Dwa_cve_2022_23960_bhb.S16 str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
19 mov x2, \_bhb_loop_count
25 subs x2, x2, #1
28 ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
Dcpu_helpers.S46 ldr x2, [x0, #CPU_RESET_FUNC]
48 cbz x2, 1f
51 br x2
73 mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
74 cmp x0, x2
75 csel x2, x2, x0, hi
86 add x1, x1, x2, lsl #3
132 ldr x2, [x0, #CPU_REG_DUMP]
133 cbz x2, 1f
134 blr x2
[all …]
Ddenver.S166 mov_imm x2, DENVER_MIDR_PN4
167 cmp x1, x2
186 mov_imm x2, DENVER_MIDR_PN4
187 cmp x1, x2
195 lsl x2, x1, #16
196 msr s3_0_c15_c0_2, x2
200 1: mrs x2, s3_0_c15_c0_2
201 lsr x2, x2, #32
203 and x2, x2, x1
204 cbnz x2, 1b
[all …]
Dcpuamu_helpers.S45 adr x2, 1f
46 add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
48 add x2, x2, x0, lsl #2 /* + "bti j" instruction */
50 br x2
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/
Dplat_sip_calls.c43 uint64_t x2, in plat_sip_handler() argument
60 if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) { in plat_sip_handler()
64 switch (x2) { in plat_sip_handler()
79 ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); in plat_sip_handler()
88 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); in plat_sip_handler()
91 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); in plat_sip_handler()
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/aarch64/
Dls1028a.S108 mov x2, x0
115 tst x0, x2
207 ldr x2, =NXP_DCFG_ADDR
211 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
215 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
256 mov x2, #1
257 lsl x2, x2, x1
262 orr x2, x2, x1
265 orr x2, x2, #ICC_SGI0R_EL1_INTID
268 msr ICC_SGI0R_EL1, x2
[all …]
/trusted-firmware-a-latest/lib/pmf/
Dpmf_smc.c19 u_register_t x2, in pmf_smc_handler() argument
30 if (!is_valid_mpidr(x2)) in pmf_smc_handler()
36 x2 = (uint32_t)x2; in pmf_smc_handler()
46 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
59 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
/trusted-firmware-a-latest/services/std_svc/
Dstd_svc_setup.c98 u_register_t x2, in std_svc_smc_handler() argument
109 x2 &= UINT32_MAX; in std_svc_smc_handler()
133 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
151 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
162 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
169 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
176 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
183 return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
191 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
196 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
[all …]
/trusted-firmware-a-latest/plat/intel/soc/common/
Dsocfpga_sip_svc_v2.c127 u_register_t x2, in sip_smc_handler_v2() argument
145 status = intel_secure_reg_read(x2, &retval); in sip_smc_handler_v2()
146 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
149 status = intel_secure_reg_write(x2, (uint32_t)x3, &retval); in sip_smc_handler_v2()
150 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
153 status = intel_secure_reg_update(x2, (uint32_t)x3, in sip_smc_handler_v2()
155 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
158 status = intel_hps_set_bridges(x2, x3); in sip_smc_handler_v2()
162 status = intel_rsu_update(x2); in sip_smc_handler_v2()
166 status = intel_v2_mbox_send_cmd(x1, (uint32_t *)x2, x3); in sip_smc_handler_v2()
[all …]
/trusted-firmware-a-latest/plat/mediatek/common/
Dmtk_sip_svc.c27 u_register_t x2, in mediatek_plat_sip_handler() argument
42 u_register_t x2, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
68 (uint32_t)x2); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
93 u_register_t x2, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/trusted-firmware-a-latest/plat/hisilicon/hikey/aarch64/
Dhikey_helpers.S48 mov_imm x2, PL011_BAUDRATE
89 ldr x2, =0xf7020000
91 str w1, [x2, #4]
93 str w1, [x2, #8]
95 str w1, [x2, #16]
97 str w1, [x2, #32]
99 mrs x2, currentel
100 and x2, x2, #0xc0
102 cmp x2, #0x04
/trusted-firmware-a-latest/plat/marvell/armada/common/
Dmrvl_sip_svc.c75 u_register_t x2, in mrvl_sip_smc_handler() argument
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
99 if (x2 >= MAX_LANE_NR) { in mrvl_sip_smc_handler()
101 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
123 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); in mrvl_sip_smc_handler()
127 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4); in mrvl_sip_smc_handler()
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/
Dplat_sip_calls.c20 u_register_t x2, in mediatek_plat_sip_handler() argument
33 ret = emi_mpu_sip_handler(x1, x2, x3); in mediatek_plat_sip_handler()
38 ret = dp_secure_handler(x1, x2, &ret_val); in mediatek_plat_sip_handler()
43 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); in mediatek_plat_sip_handler()
48 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
53 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); in mediatek_plat_sip_handler()
/trusted-firmware-a-latest/plat/hisilicon/hikey960/aarch64/
Dhikey960_helpers.S52 mov_imm x2, PL011_BAUDRATE
93 ldr x2, =0xf7020000
95 str w1, [x2, #4]
97 str w1, [x2, #8]
99 str w1, [x2, #16]
101 str w1, [x2, #32]
103 mrs x2, currentel
104 and x2, x2, #0x0c
106 cmp x2, #0x04
/trusted-firmware-a-latest/plat/marvell/armada/a3k/common/
Da3700_sip_svc.c31 u_register_t x2, in mrvl_sip_smc_handler() argument
41 __func__, smc_fid, x1, x2); in mrvl_sip_smc_handler()
45 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
54 ret = mvebu_3700_comphy_power_on(x1, x2); in mrvl_sip_smc_handler()
58 ret = mvebu_3700_comphy_power_off(x1, x2); in mrvl_sip_smc_handler()
62 ret = mvebu_3700_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()

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