Lines Matching refs:x2
151 mov x2, x0
158 tst x0, x2
196 ldr x2, =NXP_DCFG_ADDR
200 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
204 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
306 mov x2, #1
307 lsl x2, x2, x1
311 orr x2, x2, x1
313 orr x2, x2, #ICC_SGI0R_EL1_INTID
315 msr ICC_SGI0R_EL1, x2
461 mrs x2, ICC_IAR0_EL1
463 cmp x2, x3
467 msr ICC_EOIR0_EL1, x2
564 mov x2, #NXP_RESET_ADDR
565 add x2, x2, x4
566 dc cvac, x2
593 ldr x2, =NXP_DCFG_ADDR
596 str w1, [x2, x0]
599 str w1, [x2, x0]
602 str w1, [x2, x0]
628 mov x2, #DAIF_SET_MASK
631 orr x1, x1, x2
635 orr x1, x1, x2
656 ldr x2, =PMU_CLSL2FLUSHCLRR_OFFSET
657 str w0, [x3, x2]
660 ldr x2, =PMU_CLSINACTSETR_OFFSET
661 str w0, [x3, x2]
902 ldr x2, =NXP_EPU_ADDR
903 ldr w4, [x2, #EPU_EPIMCR10_OFFSET]
904 ldr w5, [x2, #EPU_EPCCR10_OFFSET]
905 ldr w6, [x2, #EPU_EPCTR10_OFFSET]
906 ldr w7, [x2, #EPU_EPGCR_OFFSET]
920 str w4, [x2, #EPU_EPIMCR10_OFFSET]
921 str w5, [x2, #EPU_EPCCR10_OFFSET]
922 str w6, [x2, #EPU_EPCTR10_OFFSET]
923 str w7, [x2, #EPU_EPGCR_OFFSET]
932 ldr x2, =NXP_GICD_ADDR
937 ldr w4, [x2, x0]
938 ldr w5, [x2, x1]
941 ldr w6, [x2, x0]
942 ldr w7, [x2, x1]
954 str w4, [x2, x0]
955 str w4, [x2, x1]
958 str w4, [x2, x0]
959 str w4, [x2, x1]
965 ldr w4, [x2, x0]
967 ldr w5, [x2, x1]
971 ldr w4, [x2, x0]
973 ldr w5, [x2, x1]
977 ldr w4, [x2, x0]
979 ldr w5, [x2, x1]
985 str w4, [x2, x0]
991 str w4, [x2, x0]
997 str w4, [x2, x0]
1002 ldr x2, =NXP_POWMGTDCR
1004 str w4, [x2]
1010 ldr x2, =PMU_IPPDEXPCR4_OFFSET
1011 ldr w7, [x3, x2]
1030 ldr x2, =BC_PSCI_BASE
1031 add x2, x2, #AUX_01_DATA
1032 str w5, [x2, #DEVDISR5_MASK_OFFSET]
1037 ldr x2, =PMU_IPSTPCR0_OFFSET
1039 str w5, [x3, x2]
1042 ldr x2, =PMU_IPSTPCR1_OFFSET
1044 str w5, [x3, x2]
1047 ldr x2, =PMU_IPSTPCR2_OFFSET
1049 str w5, [x3, x2]
1052 ldr x2, =PMU_IPSTPCR3_OFFSET
1054 str w5, [x3, x2]
1057 ldr x2, =BC_PSCI_BASE
1058 add x2, x2, #AUX_01_DATA
1059 ldr w6, [x2, #DEVDISR5_MASK_OFFSET]
1060 ldr x2, =PMU_IPSTPCR4_OFFSET
1063 str w5, [x3, x2]
1066 ldr x2, =PMU_IPSTPCR5_OFFSET
1068 str w5, [x3, x2]
1071 ldr x2, =PMU_IPSTPCR6_OFFSET
1073 str w5, [x3, x2]
1079 ldr x2, =PMU_IPSTPACK0_OFFSET
1083 ldr w0, [x3, x2]
1091 ldr x2, =PMU_IPSTPACK1_OFFSET
1095 ldr w0, [x3, x2]
1103 ldr x2, =PMU_IPSTPACK2_OFFSET
1107 ldr w0, [x3, x2]
1115 ldr x2, =PMU_IPSTPACK3_OFFSET
1119 ldr w0, [x3, x2]
1127 ldr x2, =PMU_IPSTPACK4_OFFSET
1131 ldr w0, [x3, x2]
1139 ldr x2, =PMU_IPSTPACK5_OFFSET
1143 ldr w0, [x3, x2]
1151 ldr x2, =PMU_IPSTPACK6_OFFSET
1155 ldr w0, [x3, x2]
1163 ldr x2, =NXP_DCFG_ADDR
1167 ldr w1, [x2, x0]
1170 str w1, [x2, x0]
1173 ldr w1, [x2, x0]
1176 str w1, [x2, x0]
1182 ldr w1, [x2, x0]
1185 str w1, [x2, x0]
1189 ldr w1, [x2, x0]
1193 str w1, [x2, x0]
1197 ldr w1, [x2, x0]
1201 str w1, [x2, x0]
1205 ldr w1, [x2, x0]
1208 str w1, [x2, x0]
1228 ldr x2, =NXP_DCFG_ADDR
1231 str w1, [x2, x0]
1234 str w1, [x2, x0]
1237 str w1, [x2, x0]
1324 ldr x2, =NXP_DCFG_ADDR
1325 str wzr, [x2, #DCFG_DEVDISR1_OFFSET]
1326 str wzr, [x2, #DCFG_DEVDISR3_OFFSET]
1327 str wzr, [x2, #DCFG_DEVDISR4_OFFSET]
1330 ldr x2, =NXP_POWMGTDCR
1331 ldr w4, [x2]
1333 str w4, [x2]
1337 ldp x0, x2, [sp], #16
1345 ldp x0, x2, [sp], #16
1352 ldp x0, x2, [sp], #16
1360 ldp x0, x2, [sp], #16
1365 ldp x0, x2, [sp], #16
1373 ldp x0, x2, [sp], #16
1376 ldp x2, x1, [sp], #16
1466 ldr x2, =NXP_DCFG_ADDR
1467 str w1, [x2, x0]
1551 cbz x2, 1f
1553 sub x2, x2, #1
1577 cbz x2, 1f
1579 sub x2, x2, #1
1618 ldr x2, =NXP_RESET_ADDR
1619 str w1, [x2, x0]
1676 mov x2, #DDR_SDRAM_CFG_2_FRCSR
1694 mov x2, #DDR_SLEEP_RETRY_CNT
1705 subs x2, x2, #1
1748 mov x2, #DDR_SDRAM_CFG_2_FRCSR