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/trusted-firmware-a-latest/plat/intel/soc/common/drivers/qspi/
Dcadence_qspi.h23 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
30 #define CAD_QSPI_CFG_BAUDDIV(x) (((x) << 19) & 0x780000) argument
32 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
40 #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) argument
41 #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8) argument
42 #define CAD_QSPI_DELAY_CSDADS(x) (((x) & 0xff) << 16) argument
43 #define CAD_QSPI_DELAY_CSDA(x) (((x) & 0xff) << 24) argument
46 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) argument
47 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) argument
48 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x) ((x) << 16) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/D3/
Dpfc_init_d3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/lib/compiler-rt/builtins/
Dint_math.h23 #define __has_builtin(x) 0 argument
38 #define crt_isfinite(x) _finite((x)) argument
39 #define crt_isinf(x) !_finite((x)) argument
40 #define crt_isnan(x) _isnan((x)) argument
46 #define crt_isfinite(x) __builtin_isfinite((x)) argument
48 #define crt_isfinite(x) \ argument
50 __typeof((x)) x_ = (x); \
56 #define crt_isinf(x) __builtin_isinf((x)) argument
57 #define crt_isnan(x) __builtin_isnan((x)) argument
61 #define crt_copysign(x, y) copysign((x), (y)) argument
[all …]
Dpopcountsi2.c18 su_int x = (su_int)a; in __popcountsi2() local
19 x = x - ((x >> 1) & 0x55555555); in __popcountsi2()
21 x = ((x >> 2) & 0x33333333) + (x & 0x33333333); in __popcountsi2()
23 x = (x + (x >> 4)) & 0x0F0F0F0F; in __popcountsi2()
25 x = (x + (x >> 16)); in __popcountsi2()
28 return (x + (x >> 8)) & 0x0000003F; // (6 significant bits) in __popcountsi2()
/trusted-firmware-a-latest/plat/intel/soc/agilex5/include/
Dagilex5_power_manager.h23 #define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf) argument
24 #define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf) argument
25 #define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf) argument
26 #define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1) argument
27 #define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1) argument
28 #define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8) argument
29 #define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31) argument
30 #define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff) argument
31 #define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8) argument
32 #define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16) argument
[all …]
Dagilex5_memory_controller.h25 #define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
39 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
40 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
41 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
42 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
43 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
45 #define AGX_MPFE_DDR(x) (0xf8000000 + x) argument
58 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) argument
66 #define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
70 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
[all …]
/trusted-firmware-a-latest/include/lib/libc/aarch32/
Dendian_.h68 #define __ntohl(x) ((uint32_t)(x)) argument
69 #define __ntohs(x) ((uint16_t)(x)) argument
70 #define __htonl(x) ((uint32_t)(x)) argument
71 #define __htons(x) ((uint16_t)(x)) argument
75 #define __ntohl(x) (__bswap32(x)) argument
76 #define __ntohs(x) (__bswap16(x)) argument
77 #define __htonl(x) (__bswap32(x)) argument
78 #define __htons(x) (__bswap16(x)) argument
121 #define __bswap32_constant(x) \ argument
122 ((((x) & 0xff000000U) >> 24) | \
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/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/H3/
Dpfc_init_h3_v2.c168 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
169 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
170 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
171 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
172 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
234 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
235 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
Dpfc_init_h3_v1.c166 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
167 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
168 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
169 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
170 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
171 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
172 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
173 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
232 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
233 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/M3N/
Dpfc_init_m3n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rzg/pfc/G2H/
Dpfc_init_g2h.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rzg/pfc/G2N/
Dpfc_init_g2n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/include/lib/libc/aarch64/
Dendian_.h63 #define __ntohl(x) (__bswap32(x)) argument
64 #define __ntohs(x) (__bswap16(x)) argument
65 #define __htonl(x) (__bswap32(x)) argument
66 #define __htons(x) (__bswap16(x)) argument
69 __bswap64(uint64_t x) in __bswap64() argument
74 : "=&r" (ret), "+r" (x)); in __bswap64()
103 #define __bswap32_constant(x) \ argument
104 ((((x) & 0xff000000U) >> 24) | \
105 (((x) & 0x00ff0000U) >> 8) | \
106 (((x) & 0x0000ff00U) << 8) | \
[all …]
/trusted-firmware-a-latest/plat/intel/soc/stratix10/include/
Ds10_memory_controller.h21 #define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
37 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
38 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
39 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
40 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
41 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
43 #define S10_MPFE_DDR(x) (0xf8000000 + x) argument
56 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) argument
64 #define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
68 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
[all …]
Ds10_clock_manager.h23 #define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
24 #define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
25 #define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9) argument
47 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
49 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
51 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) argument
52 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) argument
54 #define ALT_CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
81 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
82 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/M3/
Dpfc_init_m3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/drivers/renesas/rzg/pfc/G2M/
Dpfc_init_g2m.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) argument
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) argument
[all …]
/trusted-firmware-a-latest/include/lib/libc/
Dendian.h45 #define bswap16(x) __bswap16(x) argument
46 #define bswap32(x) __bswap32(x) argument
47 #define bswap64(x) __bswap64(x) argument
54 #define htobe16(x) bswap16((x)) argument
55 #define htobe32(x) bswap32((x)) argument
56 #define htobe64(x) bswap64((x)) argument
57 #define htole16(x) ((uint16_t)(x)) argument
58 #define htole32(x) ((uint32_t)(x)) argument
59 #define htole64(x) ((uint64_t)(x)) argument
61 #define be16toh(x) bswap16((x)) argument
[all …]
/trusted-firmware-a-latest/plat/intel/soc/agilex/include/
Dagilex_memory_controller.h23 #define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
38 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
39 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
40 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
41 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
42 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
44 #define AGX_MPFE_DDR(x) (0xf8000000 + x) argument
57 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) argument
65 #define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
69 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
[all …]
Dagilex_clock_manager.h80 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
81 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
82 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) argument
93 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) argument
99 #define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
107 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) argument
111 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
112 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) argument
113 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) argument
115 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) argument
[all …]
/trusted-firmware-a-latest/include/lib/libfdt/
Dlibfdt_env.h29 #define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) argument
30 #define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) argument
31 #define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ argument
32 (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))
33 #define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ argument
34 (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \
35 (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \
36 (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7))
38 static inline uint16_t fdt16_to_cpu(fdt16_t x) in fdt16_to_cpu() argument
40 return (FDT_FORCE uint16_t)CPU_TO_FDT16(x); in fdt16_to_cpu()
[all …]
/trusted-firmware-a-latest/include/drivers/cadence/
Dcdns_combo_phy.h172 #define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 argument
173 #define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 argument
174 #define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 argument
175 #define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 argument
178 #define CP_SYNC_METHOD(x) ((x) << 31) //0x1 argument
179 #define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 argument
180 #define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f argument
181 #define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 argument
182 #define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 argument
185 #define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 argument
[all …]
/trusted-firmware-a-latest/drivers/nxp/flexspi/nor/
Dfspi.h56 #define FSPI_INSTR_OPRND0(x) (x << FSPI_INSTR_OPRND0_SHIFT) argument
58 #define FSPI_INSTR_PAD0(x) ((x) << FSPI_INSTR_PAD0_SHIFT) argument
60 #define FSPI_INSTR_OPCODE0(x) ((x) << FSPI_INSTR_OPCODE0_SHIFT) argument
62 #define FSPI_INSTR_OPRND1(x) ((x) << FSPI_INSTR_OPRND1_SHIFT) argument
64 #define FSPI_INSTR_PAD1(x) ((x) << FSPI_INSTR_PAD1_SHIFT) argument
66 #define FSPI_INSTR_OPCODE1(x) ((x) << FSPI_INSTR_OPCODE1_SHIFT) argument
153 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) argument
154 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) argument
163 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) argument
164 #define FSPI_MCR0_END_CFG(x) ((x) << 2) argument
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/include/
Dimx8m_csu.h26 #define CSLx_REG(x) (IMX_CSU_BASE + ((x) / 2) * 4) argument
27 #define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8))) argument
28 #define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16)) argument
30 #define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200) argument
31 #define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) argument
32 #define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2)) argument
34 #define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218) argument
35 #define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) argument
36 #define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2)) argument
38 #define CSU_HPCONTROL_REG(x) (IMX_CSU_BASE + (((x) / 16) * 4) + 0x358) argument
[all …]
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/drivers/se/
Dse_private.h53 #define SE_STATUS(x) \ argument
54 ((x) & ((0x3U) << SE_STATUS_SHIFT))
59 #define SE_MEM_INTERFACE(x) ((x) << SE_STATUS_SHIFT) argument
65 #define SE_SECURITY_TZ_LOCK_SOFT(x) ((x) << SE_SECURITY_TZ_LOCK_SOFT_SHIFT) argument
70 #define SE_SEC_ENG_DISABLE(x)((x) << SE_SEC_ENG_DIS_SHIFT) argument
85 #define SE_CONFIG_ENC_ALG(x) \ argument
86 ((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT))
93 #define SE_CONFIG_DEC_ALG(x) \ argument
94 ((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT))
107 #define SE_CONFIG_DST(x) \ argument
[all …]

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