Searched refs:vector (Results 1 – 12 of 12) sorted by relevance
| /trusted-firmware-a-latest/plat/allwinner/common/ |
| D | sunxi_scpi_pm.c | 223 uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i); in sunxi_set_scpi_psci_ops() local
224 uint32_t offset = SUNXI_SCP_BASE - vector; in sunxi_set_scpi_psci_ops()
226 mmio_write_32(vector, offset >> 2); in sunxi_set_scpi_psci_ops()
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| D | arisc_off.S | 17 # start address in the reset vector), to be actually triggered by that
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| /trusted-firmware-a-latest/docs/design/ |
| D | reset-design.rst | 40 If the reset vector address (reflected in the reset vector base address register
51 On both the FVP and Juno platforms, the reset vector address is not programmable
105 reset vector base address, before the application processor is powered on.
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| D | interrupt-framework-design.rst | 447 initialisation. The TSP provides the address of the vector table
502 exception vector table. This is defined as the **asynchronous mode** of
600 The TSP also replaces the default exception vector table referenced through the
601 ``early_exceptions`` variable, with a vector table capable of handling FIQ and IRQ
631 When an interrupt is generated, the vector for each interrupt type is
646 at the FIQ vector. Non-secure interrupts will be signaled at the IRQ
647 vector. The platform should implement the following API to determine the
853 trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose
924 vector table when ``PSTATE.I`` and ``PSTATE.F`` bits are 0. As described earlier,
1005 exception vector handles the non-secure interrupt and returns. The return value
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| D | firmware-design.rst | 146 This stage begins execution from the platform's reset vector at EL3. The reset
151 vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
1131 location in memory where the handler is stored is called the exception vector.
1133 vector table.
1135 Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base
1136 of vector table. Refer to `AArch64 exception vector table`_
2871 .. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exc…
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| /trusted-firmware-a-latest/docs/process/ |
| D | security-hardening.rst | 34 vector.
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| /trusted-firmware-a-latest/docs/plat/ |
| D | warp7.rst | 7 the reset vector to the command-line in user-space.
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| /trusted-firmware-a-latest/docs/getting_started/ |
| D | build-options.rst | 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
727 vector address can be programmed or is fixed on the platform. It can take
755 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
761 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
872 - ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
1113 vector into TF-A by potentially allowing an attacker to inject arbitrary data.
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| /trusted-firmware-a-latest/docs/ |
| D | porting-guide.rst | 685 BL1 by default implements the reset vector where execution starts from a cold
686 or warm boot. BL31 can be optionally set as a reset vector using the
689 For each CPU, the reset vector code is responsible for the following tasks:
702 reset vector code to perform the above tasks.
1527 BL1 implements the reset vector where execution starts from after a cold or
2088 If BL31 is a reset vector, It also needs to handle the reset as specified in
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| D | change-log.md | 543 …- modify vector entry paths ([d04c04a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tru…
2216 …- support full SVE vector length ([bebcf27](https://review.trustedfirmware.org/plugins/gitiles/TF-…
7798 - Added Call Frame Information (CFI) assembler directives to the vector entries
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| /trusted-firmware-a-latest/docs/plat/arm/fvp/ |
| D | index.rst | 531 reset vector for each core.
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| /trusted-firmware-a-latest/docs/components/ |
| D | secure-partition-manager-mm.rst | 259 and installs a simple exception vector table in S-EL1 that relays a SVC request
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