Searched refs:ref_clk (Results 1 – 5 of 5) sorted by relevance
| /trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/ |
| D | s10_clock_manager.c | 203 uint32_t data32, mdiv, refclkdiv, ref_clk; in get_ref_clk() local
209 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
212 ref_clk = ALT_CLKMGR_INTOSC_HZ; in get_ref_clk()
216 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
219 ref_clk = 0; in get_ref_clk()
228 ref_clk = (ref_clk / refclkdiv) * (6 + mdiv); in get_ref_clk()
230 return ref_clk; in get_ref_clk()
234 uint32_t get_l3_clk(uint32_t ref_clk) in get_l3_clk() argument
255 noc_base_clk = ref_clk / (data32 & 0xff); in get_l3_clk()
264 uint32_t data32, ref_clk, l3_clk, l4_sys_clk; in get_wdt_clk() local
[all …]
|
| /trusted-firmware-a-latest/plat/intel/soc/agilex5/soc/ |
| D | agilex5_clock_manager.c | 136 uint32_t arefclkdiv, ref_clk; in get_ref_clk() local
142 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
145 ref_clk = CLKMGR_INTOSC_HZ; in get_ref_clk()
149 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
152 ref_clk = 0; in get_ref_clk()
158 ref_clk /= arefclkdiv; in get_ref_clk()
160 return ref_clk; in get_ref_clk()
166 uint32_t ref_clk = 0; in get_clk_freq() local
183 ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); in get_clk_freq()
185 ref_clk *= mdiv; in get_clk_freq()
[all …]
|
| /trusted-firmware-a-latest/plat/intel/soc/agilex/soc/ |
| D | agilex_clock_manager.c | 281 uint32_t arefclkdiv, ref_clk; in get_ref_clk() local
287 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
290 ref_clk = CLKMGR_INTOSC_HZ; in get_ref_clk()
294 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
297 ref_clk = 0; in get_ref_clk()
303 ref_clk /= arefclkdiv; in get_ref_clk()
305 return ref_clk; in get_ref_clk()
311 uint32_t clk_psrc, mdiv, ref_clk; in get_clk_freq() local
331 ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); in get_clk_freq()
333 ref_clk *= mdiv; in get_clk_freq()
[all …]
|
| /trusted-firmware-a-latest/drivers/marvell/comphy/ |
| D | phy-comphy-3700.c | 291 uint32_t offset, data = 0, ref_clk; in mvebu_a3700_comphy_sata_power_on() local
325 ref_clk = REF_FREF_SEL_SERDES_40MHZ; in mvebu_a3700_comphy_sata_power_on()
327 ref_clk = REF_FREF_SEL_SERDES_25MHZ; in mvebu_a3700_comphy_sata_power_on()
329 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, in mvebu_a3700_comphy_sata_power_on()
616 uint32_t mask, data, cfg, ref_clk; in mvebu_a3700_comphy_usb3_power_on() local
705 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; in mvebu_a3700_comphy_usb3_power_on()
710 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; in mvebu_a3700_comphy_usb3_power_on()
718 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; in mvebu_a3700_comphy_usb3_power_on()
812 uint32_t ref_clk; in mvebu_a3700_comphy_pcie_power_on() local
862 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; in mvebu_a3700_comphy_pcie_power_on()
[all …]
|
| /trusted-firmware-a-latest/plat/intel/soc/stratix10/include/ |
| D | s10_clock_manager.h | 97 uint32_t get_l3_clk(uint32_t ref_clk);
|
