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Searched refs:mmio_setbits_32 (Results 1 – 25 of 146) sorted by relevance

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/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1)); in spmc_init()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spmc/
Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
105 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
[all …]
/trusted-firmware-a-latest/plat/marvell/armada/a3k/common/
Dplat_pm.c271 mmio_setbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
304 mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); in a3700_set_gen_pwr_off_option()
330 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_SLEEP); in a3700_set_gen_pwr_off_option()
331 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_DEEP); in a3700_set_gen_pwr_off_option()
337 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_NB_SRAM_LKG_PD_EN); in a3700_set_gen_pwr_off_option()
346 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); in a3700_set_gen_pwr_off_option()
349 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
350 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
355 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
356 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spmc/
Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
53 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
98 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
100 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
102 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
104 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
110 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in spmc_init()
[all …]
/trusted-firmware-a-latest/plat/brcm/board/stingray/driver/
Dusb.c26 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PM_RESET_N_R); in usb_pm_rescal_init()
28 mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, RESCAL_I_RSTB); in usb_pm_rescal_init()
31 mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, in usb_pm_rescal_init()
63 mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET); in usb3h_usb2drd_init()
70 mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET); in usb3h_usb2drd_init()
116 mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET); in usb3drd_init()
123 mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET); in usb3drd_init()
176 mmio_setbits_32(USB3H_SOFT_RESET_CTRL, in usb_enable_coherence()
178 mmio_setbits_32(DRDU2_SOFT_RESET_CTRL, in usb_enable_coherence()
180 mmio_setbits_32(USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N); in usb_enable_coherence()
[all …]
Dusb_phy.c75 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO); in u2_phy_ext_fsm_power_on()
79 mmio_setbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq); in u2_phy_ext_fsm_power_on()
95 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_CTRL_CORERDY); in u2_phy_ext_fsm_power_on()
99 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_BG_PWRDWNB); in u2_phy_ext_fsm_power_on()
103 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_onin); in u2_phy_ext_fsm_power_on()
104 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_LDO_PWRDWNB); in u2_phy_ext_fsm_power_on()
108 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_okin); in u2_phy_ext_fsm_power_on()
112 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_PLL_PWRDWNB); in u2_phy_ext_fsm_power_on()
123 mmio_setbits_32(u2_phy->pll_ctrl_reg, USB2_PLL_RESETB); in u2_phy_ext_fsm_power_on()
124 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_RESETB); in u2_phy_ext_fsm_power_on()
[all …]
/trusted-firmware-a-latest/plat/brcm/board/stingray/src/
Dbl31_setup.c85 mmio_setbits_32(DMAC_M0_IDM_IO_CONTROL_DIRECT, BOOT_MANAGER_NS); in brcm_stingray_dma_pl330_init()
100 mmio_setbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); in brcm_stingray_dma_pl330_init()
115 mmio_setbits_32(idm_reset_control, 0x1); in brcm_stingray_spi_pl022_init()
211 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, in brcm_stingray_sata_init()
215 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); in brcm_stingray_sata_init()
223 mmio_setbits_32(SATA_APBT_IDM_PORT_REG(sata_port, in brcm_stingray_sata_init()
230 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
232 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
234 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
236 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
[all …]
Dihost_pm.c152 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst); in ihost_power_on_cluster()
178 mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr)); in ihost_power_on_cluster()
233 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
252 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_MODE_CONTROL, in ihost_power_on_cluster()
256 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0, in ihost_power_on_cluster()
263 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_1, in ihost_power_on_cluster()
268 mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs); in ihost_power_on_cluster()
287 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
295 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, in ihost_power_on_cluster()
299 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
[all …]
/trusted-firmware-a-latest/plat/allwinner/common/
Dsunxi_cpu_ops.c67 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), in sunxi_cpu_off()
79 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1)); in sunxi_cpu_off()
101 mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster), in sunxi_cpu_on()
108 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
110 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
112 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
120 mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0)); in sunxi_cpu_on()
128 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); in sunxi_cpu_on()
130 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0)); in sunxi_cpu_on()
132 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8)); in sunxi_cpu_on()
/trusted-firmware-a-latest/plat/mediatek/mt8183/
Dbl31_plat_setup.c42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, in platform_setup_cpu()
44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, in platform_setup_cpu()
46 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, in platform_setup_cpu()
57 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
65 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
71 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, in platform_setup_cpu()
78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, in platform_setup_cpu()
81 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, in platform_setup_cpu()
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c95 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); in config_hps_hs_before_warm_reset()
278 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
289 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
304 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_reset()
329 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), in socfpga_bridges_reset()
332 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
349 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), in socfpga_bridges_reset()
370 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_reset()
378 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0), in socfpga_bridges_reset()
399 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), in socfpga_bridges_reset()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8173/
Dbl31_plat_setup.c40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); in platform_setup_cpu()
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, in platform_setup_cpu()
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, in platform_setup_cpu()
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, in platform_setup_cpu()
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, in platform_setup_cpu()
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
/trusted-firmware-a-latest/plat/imx/imx8m/
Dgpc_common.c56 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
61 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
76 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
87 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
96 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
99 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
120 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
121 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
124 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c52 mmio_setbits_32(reg, SW_NO_WAIT_Q); in spm_disable_cpu_auto_off()
115 mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); in mcucfg_init_archstate()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
181 mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
192 mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/ddr/
Dlpddr4_dvfs.c28 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); in lpddr4_mr_write()
122 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
123 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
124 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); in lpddr4_swffc()
136 mmio_setbits_32(DDRC_PWRCTL(0), 0x60); in lpddr4_swffc()
144 mmio_setbits_32(DDRC_DBG1(0), 0x1); in lpddr4_swffc()
212 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
214 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
216 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
236 mmio_setbits_32(DDRC_DBGCMD(0), 0x10); in lpddr4_swffc()
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/dfd/mt8188/
Dplat_dfd.c24 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); in dfd_setup()
26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); in dfd_setup()
27 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
28 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
29 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
71 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
/trusted-firmware-a-latest/plat/arm/board/morello/
Dmorello_bl2_setup.c95 mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); in dmc_ecc_setup()
96 mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); in dmc_ecc_setup()
101 mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); in dmc_ecc_setup()
102 mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); in dmc_ecc_setup()
115 mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, in dmc_ecc_setup()
117 mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, in dmc_ecc_setup()
130 mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, in dmc_ecc_setup()
132 mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, in dmc_ecc_setup()
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dfd/
Dplat_dfd.c29 mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); in dfd_setup()
36 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
46 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
52 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
55 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
115 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/
Dgpc.c143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
165 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
221 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
229 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
273 mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
275 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
285 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
[all …]
/trusted-firmware-a-latest/drivers/brcm/
Dsotp.c80 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
89 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
98 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
121 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_read()
172 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
181 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
204 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
213 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
237 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
245 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/
Dgpc.c160 mmio_setbits_32(gpc_imr_offset[core_id], 1); in imx_gpc_mask_irq0()
222 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
228 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
238 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
241 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
247 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
257 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); in imx_pup_pdn_slot_config()
259 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); in imx_pup_pdn_slot_config()
261 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); in imx_pup_pdn_slot_config()
285 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); in imx_set_cluster_powerdown()
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/cpu_pm/cpcv3_2/
Dmt_smp.c32 mmio_setbits_32(pwr_ctrl->arch_addr, 1 << (16 + cpu)); in mt_smp_core_init_arch()
62 mmio_setbits_32(pwr_ctrl->pwpr, PWR_RST_B); in mt_smp_power_core_on()
66 mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON); in mt_smp_power_core_on()
72 mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON); in mt_smp_power_core_on()
Dmt_cpu_pm_cpc.c153 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); in mtk_cpc_config()
160 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); in mtk_cpc_config()
163 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); in mtk_cpc_config()
242 mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, (CPC_DBG_EN | CPC_CALC_EN)); in mtk_cpc_init()
245 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, (CPC_OFF_PRE_EN | in mtk_cpc_init()
251 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); in mtk_cpc_init()
252 mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN); in mtk_cpc_init()
/trusted-firmware-a-latest/plat/mediatek/drivers/apusys/mt8188/
Dapusys_power.c91 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0, in apu_xpu2apusys_d4_slv_en()
93 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0, in apu_xpu2apusys_d4_slv_en()
95 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0, in apu_xpu2apusys_d4_slv_en()
97 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0, in apu_xpu2apusys_d4_slv_en()
135 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA); in apusys_kernel_apusys_pwr_top_on()
174 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10)); in apu_sleep_rpc_rcx()
178 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ); in apu_sleep_rpc_rcx()
182 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ); in apu_sleep_rpc_rcx()
278 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB); in apu_pll_init()
279 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN); in apu_pll_init()
[all …]
/trusted-firmware-a-latest/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
132 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
147 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
149 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
151 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
156 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()

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