Lines Matching refs:mmio_setbits_32
143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
165 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
221 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
229 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
273 mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
275 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
285 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
296 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
299 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()