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Searched refs:mmio_clrbits_32 (Results 1 – 25 of 127) sorted by relevance

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/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c45 mmio_clrbits_32(reg, SW_NO_WAIT_Q); in spm_enable_cpu_auto_off()
58 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); in spm_set_cpu_power_off()
65 mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q); in spm_enable_cluster_auto_off()
66 mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0)); in spm_enable_cluster_auto_off()
68 mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN); in spm_enable_cluster_auto_off()
70 mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON); in spm_enable_cluster_auto_off()
168 mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
172 mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/ddr/
Dlpddr4_dvfs.c59 mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); in lpddr4_swffc()
64 mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1); in lpddr4_swffc()
111 mmio_clrbits_32(DDRC_DERATEEN(0), 0x1); in lpddr4_swffc()
115 mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1); in lpddr4_swffc()
119 mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1); in lpddr4_swffc()
127 mmio_clrbits_32(DDRC_PWRCTL(0), 0x1); in lpddr4_swffc()
203 mmio_clrbits_32(DDRC_DFIMISC(0), 0x20); in lpddr4_swffc()
244 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
246 mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
248 mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30)); in lpddr4_swffc()
[all …]
Dclock.c78 mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30); in dram_pll_init()
88 mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); in dram_pll_init()
124 mmio_clrbits_32(DRAM_PLL_CTRL, BIT(16)); in dram_pll_init()
/trusted-firmware-a-latest/plat/allwinner/common/
Dsunxi_cpu_ops.c64 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_off()
71 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_off()
76 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8)); in sunxi_cpu_off()
82 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); in sunxi_cpu_off()
97 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
99 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
106 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); in sunxi_cpu_on()
115 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0)); in sunxi_cpu_on()
117 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0)); in sunxi_cpu_on()
126 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(1)); in sunxi_cpu_on()
/trusted-firmware-a-latest/plat/mediatek/drivers/cpu_pm/cpcv3_2/
Dmt_smp.c34 mmio_clrbits_32(pwr_ctrl->arch_addr, 1 << (16 + cpu)); in mt_smp_core_init_arch()
52 mmio_clrbits_32(pwr_ctrl->pwpr, RESETPWRON_CONFIG); in mt_smp_power_core_on()
71 mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON); in mt_smp_power_core_on()
84 mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON); in mt_smp_power_core_off()
91 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in mt_smp_init()
92 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in mt_smp_init()
/trusted-firmware-a-latest/plat/allwinner/sun50i_a64/
Dsunxi_power.c46 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); in sunxi_turn_off_soc()
47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); in sunxi_turn_off_soc()
53 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); in sunxi_turn_off_soc()
61 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); in sunxi_turn_off_soc()
62 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); in sunxi_turn_off_soc()
76 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); in sunxi_turn_off_soc()
79 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); in sunxi_turn_off_soc()
82 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); in sunxi_turn_off_soc()
83 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); in sunxi_turn_off_soc()
/trusted-firmware-a-latest/plat/imx/imx8m/
Dgpc_common.c69 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
74 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
85 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
102 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
105 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
126 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
127 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
130 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
143 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); in imx_set_cluster_standby()
173 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); in imx_set_cluster_powerdown()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spmc/
Dmtspmc.c25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
55 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
106 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
107 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
108 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
137 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); in spm_poweron_cpu()
149 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spmc/
Dmtspmc.c25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
101 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
102 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
103 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
129 mmio_clrbits_32(cpu_pwr_con, PWR_ON); in spm_poweron_cpu()
143 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc.c25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
53 mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
109 mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
110 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
111 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
137 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); in spm_poweron_cpu()
141 mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3)); in spm_poweron_cpu()
154 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
/trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c160 mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
161 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
162 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
163 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
164 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
165 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
166 mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
168 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
169 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
170 mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK); in init_hard_memory_controller()
[all …]
/trusted-firmware-a-latest/plat/brcm/board/stingray/driver/
Dusb_phy.c83 mmio_clrbits_32(u2_phy->phy_ctrl_reg, in u2_phy_ext_fsm_power_on()
116 mmio_clrbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO); in u2_phy_ext_fsm_power_on()
119 mmio_clrbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq); in u2_phy_ext_fsm_power_on()
145 mmio_clrbits_32(base + USB3H_U2PLL_CTRL, in usb3h_u2_phy_power_on()
170 mmio_clrbits_32(base + USB3H_U3PHY_PLL_CTRL, in usb3h_u3_phy_power_on()
201 mmio_clrbits_32(base + DRDU3_U2PLL_CTRL, in drdu3_u2_phy_power_on()
228 mmio_clrbits_32(base + DRDU3_U3PHY_PLL_CTRL, in drdu3_u3_phy_power_on()
259 mmio_clrbits_32(base + DRDU2_U2PLL_CTRL, in drdu2_u2_phy_power_on()
282 mmio_clrbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL, in u3h_u2drd_phy_reset()
288 mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
[all …]
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c22 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST), in deassert_peripheral_reset()
44 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
55 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in deassert_peripheral_reset()
79 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), in deassert_peripheral_reset()
309 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
314 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
319 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); in socfpga_bridges_reset()
345 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0), in socfpga_bridges_reset()
374 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), in socfpga_bridges_reset()
382 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); in socfpga_bridges_reset()
[all …]
Dsocfpga_emac.c29 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), in socfpga_emac_init()
34 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), in socfpga_emac_init()
/trusted-firmware-a-latest/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
119 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
120 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
153 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
154 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
Dhikey960_bl2_setup.c92 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
97 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
98 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
124 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
130 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
131 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
132 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
/trusted-firmware-a-latest/drivers/brcm/
Dsotp.c84 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
106 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
124 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
177 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
185 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
216 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
248 mmio_clrbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
252 mmio_clrbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/
Dgpc.c140 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
163 mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
175 mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
245 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
252 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
263 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
331 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | in imx_gpc_init()
373 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
374 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()
/trusted-firmware-a-latest/plat/mediatek/mt8173/
Dscu.c25 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in enable_scu()
28 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in enable_scu()
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/
Dgpc.c162 mmio_clrbits_32(gpc_imr_offset[core_id], 1); in imx_gpc_mask_irq0()
244 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
266 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
267 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
268 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
301 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
312 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown()
350 mmio_clrbits_32(IMX_ANAMIX_BASE + imx8mq_pll[i].reg, in imx_anamix_override()
429 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init()
436 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
[all …]
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/m0/src/
Dsuspend.c27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main()
55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
Ddram.c31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c258 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training()
304 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training()
352 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training()
385 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training()
399 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training()
420 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training()
424 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
622 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
641 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
691 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()
[all …]
/trusted-firmware-a-latest/plat/intel/soc/common/drivers/ccu/
Dncore_ccu.c49 mmio_clrbits_32(dir_sf_en, BIT(sf)); in directory_init()
86 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), in bypass_ocram_firewall()
88 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2), in bypass_ocram_firewall()
90 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3), in bypass_ocram_firewall()
92 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), in bypass_ocram_firewall()
/trusted-firmware-a-latest/plat/mediatek/mt8173/drivers/mtcmos/
Dmtcmos.c138 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); in mtcmos_ctrl_little_off()
144 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off()
146 mmio_clrbits_32(reg_pwr_con, PWR_ON); in mtcmos_ctrl_little_off()
147 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); in mtcmos_ctrl_little_off()
270 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()

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