Lines Matching refs:mmio_clrbits_32
162 mmio_clrbits_32(gpc_imr_offset[core_id], 1); in imx_gpc_mask_irq0()
244 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
266 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
267 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
268 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); in imx_pup_pdn_slot_config()
301 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
312 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); in imx_set_cluster_powerdown()
350 mmio_clrbits_32(IMX_ANAMIX_BASE + imx8mq_pll[i].reg, in imx_anamix_override()
429 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); in imx_gpc_init()
436 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); in imx_gpc_init()
437 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); in imx_gpc_init()