| /trusted-firmware-a-latest/services/std_svc/sdei/ |
| D | sdei_event.c | 24 const sdei_mapping_t *mapping; in get_event_entry() local
34 mapping = SDEI_PRIVATE_MAPPING(); in get_event_entry()
35 idx = MAP_OFF(map, mapping); in get_event_entry()
38 base_idx = plat_my_core_pos() * ((unsigned int) mapping->num_maps); in get_event_entry()
47 mapping = SDEI_SHARED_MAPPING(); in get_event_entry()
48 idx = MAP_OFF(map, mapping); in get_event_entry()
60 const sdei_mapping_t *mapping; in find_event_map_by_intr() local
69 mapping = shared ? SDEI_SHARED_MAPPING() : SDEI_PRIVATE_MAPPING(); in find_event_map_by_intr()
70 iterate_mapping(mapping, i, map) { in find_event_map_by_intr()
84 const sdei_mapping_t *mapping; in find_event_map() local
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| D | sdei_main.c | 863 const sdei_mapping_t *mapping; in sdei_shared_reset() local
887 for_each_mapping_type(i, mapping) { in sdei_shared_reset()
888 iterate_mapping(mapping, j, map) { in sdei_shared_reset()
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| /trusted-firmware-a-latest/docs/plat/ |
| D | imx8m.rst | 83 There is a special case of mapping the DRAM: entire DRAM available on the
86 Mapping the entire DRAM allows the usage of 2MB block mapping in Level-2
88 Level-3 PTE mapping is used instead then additional PTEs would be required,
92 family it should rather be avoided creating additional Level-3 mapping and
93 introduce more PTEs, hence the implementation uses Level-2 mapping which
96 The reason for the MT_RW attribute mapping scheme is the fact that the SMC
102 Therefore, DRAM mapping is done with MT_RW attributes, as it is required for
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| D | allwinner.rst | 101 The mapping we use on those SoCs is as follows:
133 SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
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| D | rpi3.rst | 234 mapping required for an UEFI firmware payload. These changes are needed
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| /trusted-firmware-a-latest/docs/components/ |
| D | xlat-tables-lib-v2-design.rst | 19 #. Support for dynamic mapping and unmapping of regions, even while the MMU is
35 support dynamic mapping. ``lib/xlat_mpu``, which configures Arm's MPU
69 - its mapping granularity (optional).
85 The granularity controls the translation table level to go down to when mapping
92 contains 512 entries, each mapping 4KB).
103 then they might enforce a 4KB mapping granularity for this 2MB region from the
108 library will choose the mapping granularity for this region as it sees fit (more
109 details can be found in `The memory mapping algorithm`_ section below).
187 The library optionally supports dynamic memory mapping. This feature may be
190 When dynamic memory mapping is enabled, the library categorises mmap regions as
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| D | granule-protection-tables-design.rst | 50 mapping is used, or a level 0 entry can link to a level 1 table where relatively
52 step mapping. The type of mapping used for each PAS is determined by the user
98 #. The desired attributes of this memory region (mapping type, PAS type)
111 imply, ``GPT_MAP_REGION_BLOCK`` creates a region using only L0 mapping while
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| /trusted-firmware-a-latest/lib/romlib/ |
| D | romlib_generator.py | 99 def build_template(self, name, mapping=None, remove_comment=False): argument
120 return template.substitute(mapping)
254 mapping = {"jmptbl_address": matching_symbol.group(1)}
257 output_file.write(self.build_template("jmptbl_glob_var.S", mapping))
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| /trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/ |
| D | dimm.c | 234 if (spd->mapping[i] == udimm_rc_e_dq[i]) { in cal_dimm_params()
238 ptr = (unsigned char *)&spd->mapping[i]; in cal_dimm_params()
391 pdimm->dq_mapping[i] = spd->mapping[i]; in cal_dimm_params()
395 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; in cal_dimm_params()
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-3.rst | 31 mapping specifying both ``MT_RO`` and ``MT_EXECUTE_NEVER`` should result in a
49 would only manifest itself for device memory mapped as RO; use of this mapping
50 is considered rare, although the upstream QEMU platform uses this mapping when
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| /trusted-firmware-a-latest/include/drivers/nxp/ddr/ |
| D | dimm.h | 93 unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ member
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1028a/ |
| D | soc.def | 79 # Enable dynamic memory mapping
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ |
| D | soc.def | 88 # enable dynamic memory mapping
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1043a/ |
| D | soc.def | 88 # enable dynamic memory mapping
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| /trusted-firmware-a-latest/fdts/ |
| D | stm32mp13-ddr3-1x4Gb-1066-binF.dtsi | 16 * address mapping : RBC
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| D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 13 * Address mapping type: RBC
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| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 13 * Address mapping type: RBC
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| D | stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 15 * address mapping : RBC
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| D | stm32mp15-ddr3-1x2Gb-1066-binG.dtsi | 13 * Address mapping type: RBC
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| /trusted-firmware-a-latest/plat/nxp/soc-lx2160a/ |
| D | soc.def | 115 # enable dynamic memory mapping
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| /trusted-firmware-a-latest/docs/plat/st/ |
| D | stm32mp2.rst | 27 Memory mapping
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| D | stm32mp1.rst | 49 Memory mapping
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| /trusted-firmware-a-latest/docs/plat/marvell/armada/ |
| D | porting.rst | 26 This file describes the SoC physical memory mapping to be used for the CCU,
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| /trusted-firmware-a-latest/docs/design/ |
| D | interrupt-framework-design.rst | 175 mapping between the type and signal is known only to the platform. The framework
185 Effect of mapping of several interrupt types to one signal
248 The ``scr_el3[2]`` field also stores the routing model but as a mapping of the
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| /trusted-firmware-a-latest/docs/ |
| D | change-log.md | 768 …- add device mapping for coherent memory ([cef2e92](https://review.trustedfirmware.org/plugins/git…
871 …- add missing irq mapping for wakeup src ([06b9c4c](https://review.trustedfirmware.org/plugins/git…
2424 …- change BL33 memory mapping ([10f6dc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tr…
2719 …- mapping Run-time UART to IOFPGA UART0 ([4a81e91](https://review.trustedfirmware.org/plugins/giti…
3022 …- fix firmware buffer re-mapping issue ([742c23a](https://review.trustedfirmware.org/plugins/gitil…
3419 …- update memory mapping for STM32MP13 ([48ede66](https://review.trustedfirmware.org/plugins/gitile…
3944 …- restrict DEVICE2 mapping in BL2 ([db3e0ec](https://review.trustedfirmware.org/plugins/gitiles/TF…
4165 …- ddr: corrects mapping of HNFs nodes ([e3a2349](https://review.trustedfirmware.org/plugins/gitile…
4231 …- correct memory mapping for STM32MP13 ([99605fb](https://review.trustedfirmware.org/plugins/gitil…
5601 - Refactored header file inclusions and inclusion of memory mapping
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