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Searched refs:level (Results 1 – 25 of 90) sorted by relevance

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/trusted-firmware-a-latest/plat/common/
Dplat_log_common.c18 unsigned int level; in plat_log_get_prefix() local
21 level = LOG_LEVEL_ERROR; in plat_log_get_prefix()
23 level = LOG_LEVEL_VERBOSE; in plat_log_get_prefix()
25 level = log_level; in plat_log_get_prefix()
28 return plat_prefix_str[(level / 10U) - 1U]; in plat_log_get_prefix()
/trusted-firmware-a-latest/plat/mediatek/lib/mtk_init/
Dmtk_init.c19 void mtk_init_one_level(uint32_t level) in mtk_init_one_level() argument
24 if (level >= MTK_INIT_LVL_MAX) { in mtk_init_one_level()
25 ERROR("invalid level:%u\n", level); in mtk_init_one_level()
29 INFO("init calling level:%u\n", level); in mtk_init_one_level()
30 for (entry = initcall_list[level]; in mtk_init_one_level()
31 (entry != NULL) && (entry < initcall_list[level + 1]); in mtk_init_one_level()
/trusted-firmware-a-latest/lib/xlat_tables_v2/
Dxlat_tables_utils.c141 unsigned int level) in xlat_tables_print_internal() argument
143 assert(level <= XLAT_TABLE_LEVEL_MAX); in xlat_tables_print_internal()
148 size_t level_size = XLAT_BLOCK_SIZE(level); in xlat_tables_print_internal()
166 level_spacers[level], in xlat_tables_print_internal()
175 level_spacers[level], in xlat_tables_print_internal()
186 (level < XLAT_TABLE_LEVEL_MAX)) { in xlat_tables_print_internal()
194 level_spacers[level], in xlat_tables_print_internal()
201 XLAT_TABLE_ENTRIES, level + 1U); in xlat_tables_print_internal()
204 level_spacers[level], table_idx_va, in xlat_tables_print_internal()
218 level_spacers[level], invalid_row_count - 1); in xlat_tables_print_internal()
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Dxlat_tables_core.c108 unsigned long long addr_pa, unsigned int level) in xlat_desc() argument
115 assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U); in xlat_desc()
122 desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; in xlat_desc()
265 const unsigned int level) in xlat_tables_find_start_va() argument
271 table_idx_va = mm->base_va & ~XLAT_BLOCK_MASK(level); in xlat_tables_find_start_va()
285 const unsigned int level) in xlat_tables_va_to_index() argument
287 return (unsigned int)((va - table_base_va) >> XLAT_ADDR_SHIFT(level)); in xlat_tables_va_to_index()
298 const unsigned int level, const uint64_t desc_type) in xlat_tables_unmap_region_action() argument
307 if (level == 3U) { in xlat_tables_unmap_region_action()
342 assert(level < 3U); in xlat_tables_unmap_region_action()
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Dxlat_tables_private.h84 unsigned long long addr_pa, unsigned int level);
/trusted-firmware-a-latest/include/lib/xlat_tables/
Dxlat_tables_defs.h103 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ argument
104 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
106 #define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) argument
108 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) argument
110 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) argument
115 #define XLAT_TABLE_IDX(virtual_addr, level) \ argument
116 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
/trusted-firmware-a-latest/lib/xlat_tables/
Dxlat_tables_common.c29 #define get_level_spacer(level) \ argument
30 (((level) == U(0)) ? LVL0_SPACER : \
31 (((level) == U(1)) ? LVL1_SPACER : \
32 (((level) == U(2)) ? LVL2_SPACER : LVL3_SPACER)))
190 unsigned int level) in mmap_desc() argument
196 assert((addr_pa & XLAT_BLOCK_MASK(level)) == 0U); in mmap_desc()
203 desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; in mmap_desc()
327 unsigned int level) in init_xlation_table_inner() argument
329 assert((level >= XLAT_TABLE_LEVEL_MIN) && in init_xlation_table_inner()
330 (level <= XLAT_TABLE_LEVEL_MAX)); in init_xlation_table_inner()
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Dxlat_tables_private.h38 unsigned int level, uintptr_t *max_va,
/trusted-firmware-a-latest/plat/marvell/armada/a3k/common/
Da3700_ea.c26 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_ea_handler() local
63 if (level < MODE_EL3 && ea_reason == ERROR_EA_ASYNC && in plat_ea_handler()
68 syndrome, read_mpidr_el1(), get_el_str(level)); in plat_ea_handler()
/trusted-firmware-a-latest/lib/psci/
Dpsci_setup.c45 unsigned char level) in psci_init_pwr_domain_node() argument
47 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()
50 psci_non_cpu_pd_nodes[node_idx].level = level; in psci_init_pwr_domain_node()
129 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree() local
140 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
159 (unsigned char)level); in populate_power_domain_tree()
167 level--; in populate_power_domain_tree()
170 if (level == (int) PSCI_CPU_PWR_LVL) in populate_power_domain_tree()
Dpsci_common.c793 unsigned int level; in psci_acquire_pwr_domain_locks() local
796 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { in psci_acquire_pwr_domain_locks()
797 parent_idx = parent_nodes[level - 1U]; in psci_acquire_pwr_domain_locks()
811 unsigned int level; in psci_release_pwr_domain_locks() local
814 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { in psci_release_pwr_domain_locks()
815 parent_idx = parent_nodes[level - 1U]; in psci_release_pwr_domain_locks()
1121 psci_non_cpu_pd_nodes[idx].level, in psci_print_power_domain_map()
/trusted-firmware-a-latest/plat/brcm/board/common/
Dbcm_elog.c39 unsigned int level; member
98 int bcm_elog_init(void *base, uint32_t size, unsigned int level) in bcm_elog_init() argument
106 elog->level = level / 10; in bcm_elog_init()
196 unsigned int level = fmt[0]; in bcm_elog() local
198 if (!elog->is_active || level > elog->level) in bcm_elog()
201 prefix_str = plat_log_get_prefix(level); in bcm_elog()
/trusted-firmware-a-latest/lib/xlat_tables/aarch32/
Dnonlpae_tables.c293 unsigned int level) in mmap_desc() argument
297 switch (level) { in mmap_desc()
335 if (level == 2U) { in mmap_desc()
397 unsigned int level) in init_xlation_table_inner() argument
399 unsigned int level_size_shift = (level == 1U) ? in init_xlation_table_inner()
402 unsigned int level_index_mask = (level == 1U) ? in init_xlation_table_inner()
406 assert((level == 1U) || (level == 2U)); in init_xlation_table_inner()
408 VERBOSE("init xlat table at %p (level%1u)\n", (void *)table, level); in init_xlation_table_inner()
420 if (level == 2U) { in init_xlation_table_inner()
421 printf(" 0x%lx %x " + 6 - 2 * level, in init_xlation_table_inner()
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/trusted-firmware-a-latest/include/plat/brcm/common/
Dbcm_elog.h15 int bcm_elog_init(void *base, uint32_t size, unsigned int level);
21 unsigned int level) in bcm_elog_init() argument
/trusted-firmware-a-latest/docs/perf/
Dpsci-performance-juno.rst72 ``CPU_SUSPEND`` to deepest power level
75 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
94 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
113 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
132 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
151 ``CPU_SUSPEND`` to power level 0
154 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
173 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
192 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
210 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
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Dpsci-performance-n1sdp.rst92 ``CPU_SUSPEND`` to deepest power level
95 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
110 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
125 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
140 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
155 ``CPU_SUSPEND`` to power level 0
158 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
175 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
190 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
206 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
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/trusted-firmware-a-latest/plat/arm/board/fvp/aarch64/
Dfvp_ea.c35 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_ea_handler() local
39 if ((level < MODE_EL3) && (fault_address == TEST_ADDRESS)) { in plat_ea_handler()
/trusted-firmware-a-latest/lib/zlib/
Dzlib.h707 int level,
1249 int level);
1384 ZEXTERN int ZEXPORT gzsetparams(gzFile file, int level, int strategy);
1784 ZEXTERN int ZEXPORT deflateInit_(z_streamp strm, int level,
1788 ZEXTERN int ZEXPORT deflateInit2_(z_streamp strm, int level, int method,
1799 # define z_deflateInit(strm, level) \ argument
1800 deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))
1803 # define z_deflateInit2(strm, level, method, windowBits, memLevel, strategy) \ argument
1804 deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\
1813 # define deflateInit(strm, level) \ argument
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/trusted-firmware-a-latest/plat/common/aarch64/
Dplat_common.c93 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_default_ea_handler() local
97 read_mpidr_el1(), get_el_str(level)); in plat_default_ea_handler()
/trusted-firmware-a-latest/fdts/
Da5ds.dts30 next-level-cache = <&L2>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
61 cache-level = <2>;
/trusted-firmware-a-latest/docs/components/
Dgranule-protection-tables-design.rst46 The GPT can function as either a 1 level or 2 level lookup depending on how a
47 PAS region is configured. The first step is the level 0 table, each entry in the
48 level 0 table controls access to a relatively large region in memory (block
50 mapping is used, or a level 0 entry can link to a level 1 table where relatively
64 which is how large each level 1 granule is, and L0GPTSZ (level 0 GPT size) which
65 determines how much physical memory is governed by each level 0 entry. A granule
119 the level 0 tables and ``gpt_init_pas_l1_tables`` takes an address and size for
120 building the level 1 tables which are linked from level 0 descriptors. The
122 its level 0 table in SRAM and its level 1 table(s) in DRAM.
145 #. Firmware must call ``gpt_init_l0_tables`` to initialize the level 0 tables to
Dexception-handling.rst98 for more than one priority level.
107 A priority level is *active* when a handler at that priority level is currently
111 The priority level is likewise implicitly deactivated when the interrupt
118 activate and deactivate the respective priority level as and when they're
126 explicit. The |EHF| therefore disallows for lower priority level to be activated
127 whilst a higher priority level is active, and would result in a panic.
129 level when a higher priority level is active.
131 In essence, priority level activation and deactivation conceptually works like a
143 top-level handler for interrupts that target EL3, as described in the
168 handlers for them. A given priority level can be assigned to only one handler. A
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Dxlat-tables-lib-v2-design.rst17 translation regime than the exception level the library code is executing at;
85 The granularity controls the translation table level to go down to when mapping
90 - using a single level-2 translation table entry;
91 - using a level-2 intermediate entry to a level-3 translation table (which
97 page tables to refine the mappings. If a single level-2 entry has been used
98 here, a level-3 table will need to be allocated on the fly and the level-2
99 modified to point to this new level-3 table. This has a performance cost at
125 translation regime than the exception level the library code is executing at.
134 to the translation regime of the current exception level. Additional contexts
155 excluding the initial lookup level translation table, which is always
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/trusted-firmware-a-latest/plat/imx/imx8m/include/
Dimx8m_csu.h60 #define CSU_CSLx(i, level, lk) \ argument
61 {CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
/trusted-firmware-a-latest/docs/getting_started/
Dimage-terminology.rst22 - Previously, the format for 3rd level images had 2 forms; ``BL3`` was either
65 required to load and authenticate all 3rd level firmware images into their
82 abbreviation should be avoided; use the recommended **Other AP 3rd level
90 Other AP 3rd level images: ``AP_BL3_XXX``
93 The abbreviated names of the existing 3rd level images imply a load/execution
97 but new 3rd level images should be suffixed with an underscore followed by text
100 In systems where 3rd level images are provided by different vendors, the
132 SCP needs to load/authenticate multiple 3rd level images in future.
153 secure and normal world. The "level" of the BL image is relative to the world
184 underscore and the level of the firmware image.

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