Lines Matching refs:level

72 ``CPU_SUSPEND`` to deepest power level
75 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
94 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
113 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
132 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
151 ``CPU_SUSPEND`` to power level 0
154 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
173 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
192 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
210 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
232 core to the deepest power level.
325 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
357 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
376 There is no lock contention in TF generic code at power level 0 but the large
387 require locks at power level 0.
390 the cache associated with power level 0 is flushed (L1).
392 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
413 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
422 level 0, which only requires L1 cache flush.
424 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
444 only necessary to flush the cache to power level 0 (L1). This is the best case
454 ``CPU_OFF`` on all non-lead CPUs in sequence then ``CPU_SUSPEND`` on lead CPU to deepest power level
461 2. Program wake up timer and suspend the lead CPU to the deepest power level.
483 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
486 lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
525 effects, given that these measurements are at the nano-second level.