Home
last modified time | relevance | path

Searched refs:ctx (Results 1 – 25 of 76) sorted by relevance

1234

/trusted-firmware-a-latest/lib/el3_runtime/aarch64/
Dcontext_mgmt.c45 static void manage_extensions_nonsecure(cpu_context_t *ctx);
46 static void manage_extensions_secure(cpu_context_t *ctx);
49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) in setup_el1_context() argument
93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); in setup_el1_context()
103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); in setup_el1_context()
110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) in setup_secure_context() argument
115 state = get_el3state_ctx(ctx); in setup_secure_context()
150 setup_el1_context(ctx, ep); in setup_secure_context()
153 manage_extensions_secure(ctx); in setup_secure_context()
173 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) in setup_realm_context() argument
[all …]
/trusted-firmware-a-latest/drivers/st/crypto/
Dstm32_saes.c209 static int saes_start(struct stm32_saes_context *ctx) in saes_start() argument
214 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_start()
216 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_start()
219 while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) { in saes_start()
229 static void saes_end(struct stm32_saes_context *ctx, int prev_error) in saes_end() argument
233 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_end()
235 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); in saes_end()
239 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); in saes_end()
242 static void saes_write_iv(struct stm32_saes_context *ctx) in saes_write_iv() argument
245 if (does_chaining_mode_need_iv(ctx->cr)) { in saes_write_iv()
[all …]
/trusted-firmware-a-latest/drivers/nxp/crypto/caam/src/auth/
Dhash.c42 int hash_init(enum hash_algo algo, void **ctx) in hash_init() argument
48 *ctx = &glbl_ctx; in hash_init()
67 struct hash_ctx *ctx = context; in hash_update() local
69 if (ctx->sg_num >= MAX_SG) { in hash_update()
71 ctx->active = false; in hash_update()
76 if (ctx->algo != algo) { in hash_update()
78 ctx->active = false; in hash_update()
88 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, in hash_update()
91 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); in hash_update()
93 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uintptr_t) data_ptr); in hash_update()
[all …]
Drsa.c41 struct rsa_context ctx __aligned(CACHE_WRITEBACK_GRANULE); in rsa_public_verif_sec()
47 memset(&ctx, 0, sizeof(struct rsa_context)); in rsa_public_verif_sec()
49 ctx.pkin.a = sign; in rsa_public_verif_sec()
50 ctx.pkin.a_siz = klen; in rsa_public_verif_sec()
51 ctx.pkin.n = rsa_pub_key; in rsa_public_verif_sec()
52 ctx.pkin.n_siz = klen; in rsa_public_verif_sec()
53 ctx.pkin.e = rsa_pub_key + klen; in rsa_public_verif_sec()
54 ctx.pkin.e_siz = klen; in rsa_public_verif_sec()
56 cnstr_jobdesc_pkha_rsaexp(jobdesc.desc, &ctx.pkin, to, klen); in rsa_public_verif_sec()
61 flush_dcache_range((uintptr_t)&ctx.pkin, sizeof(ctx.pkin)); in rsa_public_verif_sec()
/trusted-firmware-a-latest/lib/xlat_tables_v2/
Dxlat_tables_core.c43 static int xlat_table_get_index(const xlat_ctx_t *ctx, const uint64_t *table) in xlat_table_get_index() argument
45 for (int i = 0; i < ctx->tables_num; i++) in xlat_table_get_index()
46 if (ctx->tables[i] == table) in xlat_table_get_index()
59 static uint64_t *xlat_table_get_empty(const xlat_ctx_t *ctx) in xlat_table_get_empty() argument
61 for (int i = 0; i < ctx->tables_num; i++) in xlat_table_get_empty()
62 if (ctx->tables_mapped_regions[i] == 0) in xlat_table_get_empty()
63 return ctx->tables[i]; in xlat_table_get_empty()
69 static void xlat_table_inc_regions_count(const xlat_ctx_t *ctx, in xlat_table_inc_regions_count() argument
72 int idx = xlat_table_get_index(ctx, table); in xlat_table_inc_regions_count()
74 ctx->tables_mapped_regions[idx]++; in xlat_table_inc_regions_count()
[all …]
Dxlat_tables_utils.c31 void xlat_tables_print(__unused xlat_ctx_t *ctx) in xlat_tables_print() argument
53 static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc) in xlat_desc_print() argument
56 int xlat_regime = ctx->xlat_regime; in xlat_desc_print()
139 static void xlat_tables_print_internal(xlat_ctx_t *ctx, uintptr_t table_base_va, in xlat_tables_print_internal() argument
199 xlat_tables_print_internal(ctx, table_idx_va, in xlat_tables_print_internal()
207 xlat_desc_print(ctx, desc); in xlat_tables_print_internal()
222 void xlat_tables_print(xlat_ctx_t *ctx) in xlat_tables_print() argument
227 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_tables_print()
229 } else if (ctx->xlat_regime == EL2_REGIME) { in xlat_tables_print()
232 assert(ctx->xlat_regime == EL3_REGIME); in xlat_tables_print()
[all …]
/trusted-firmware-a-latest/plat/qti/qtiseclib/src/
Dqtiseclib_cb_interface.c132 void *ctx; in qtiseclib_cb_get_ns_ctx() local
134 ctx = cm_get_context(NON_SECURE); in qtiseclib_cb_get_ns_ctx()
135 if (ctx) { in qtiseclib_cb_get_ns_ctx()
141 read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in qtiseclib_cb_get_ns_ctx()
142 qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3); in qtiseclib_cb_get_ns_ctx()
145 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SPSR_EL1); in qtiseclib_cb_get_ns_ctx()
147 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_ELR_EL1); in qtiseclib_cb_get_ns_ctx()
148 qti_ns_ctx->sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SP_EL1); in qtiseclib_cb_get_ns_ctx()
150 qti_ns_ctx->x0 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0); in qtiseclib_cb_get_ns_ctx()
151 qti_ns_ctx->x1 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1); in qtiseclib_cb_get_ns_ctx()
[all …]
/trusted-firmware-a-latest/plat/arm/css/sgi/ras/
Dsgi_ras_cpu.c55 void *ctx; in populate_cpu_err_data() local
57 ctx = cm_get_context(security_state); in populate_cpu_err_data()
65 cpu_info->ErrCtxEl1Reg[0] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
67 cpu_info->ErrCtxEl1Reg[1] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
69 cpu_info->ErrCtxEl1Reg[2] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
72 cpu_info->ErrCtxEl1Reg[4] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
76 cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
78 cpu_info->ErrCtxEl1Reg[8] = read_ctx_reg(get_gpregs_ctx(ctx), in populate_cpu_err_data()
80 cpu_info->ErrCtxEl1Reg[9] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
82 cpu_info->ErrCtxEl1Reg[10] = read_ctx_reg(get_el1_sysregs_ctx(ctx), in populate_cpu_err_data()
[all …]
/trusted-firmware-a-latest/lib/xlat_mpu/
Dxlat_mpu_core.c158 static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm) in mmap_add_region_check() argument
177 if (end_pa > ctx->pa_max_address) { in mmap_add_region_check()
181 if (ctx->mmap[ctx->mmap_num - 1].size != 0U) { in mmap_add_region_check()
185 for (const mmap_region_t *mm_cursor = ctx->mmap; in mmap_add_region_check()
247 void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm) in mmap_add_region_ctx() argument
249 mmap_region_t *mm_cursor = ctx->mmap, *mm_destination; in mmap_add_region_ctx()
250 const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num; in mmap_add_region_ctx()
262 assert(!ctx->initialized); in mmap_add_region_ctx()
264 ret = mmap_add_region_check(ctx, mm); in mmap_add_region_ctx()
274 mm_last = ctx->mmap; in mmap_add_region_ctx()
[all …]
Dxlat_mpu_utils.c32 void xlat_tables_print(__unused xlat_ctx_t *ctx) in xlat_tables_print() argument
39 static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx) in xlat_tables_print_internal() argument
78 void xlat_tables_print(__unused xlat_ctx_t *ctx) in xlat_tables_print() argument
80 xlat_tables_print_internal(ctx); in xlat_tables_print()
/trusted-firmware-a-latest/drivers/amlogic/crypto/
Dsha_dma.c112 static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len, in asd_compute_sha() argument
118 .dst = (uint32_t)(uintptr_t)ctx->digest, in asd_compute_sha()
123 assert((uintptr_t)ctx->digest == (uintptr_t)desc.dst); in asd_compute_sha()
130 if (ctx->started == 0) { in asd_compute_sha()
132 ctx->started = 1; in asd_compute_sha()
136 ctx->started = 0; in asd_compute_sha()
138 if (ctx->mode == ASM_SHA224) in asd_compute_sha()
150 flush_dcache_range((uintptr_t)ctx->digest, SHA256_HASHSZ); in asd_compute_sha()
153 void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len) in asd_sha_update() argument
157 if (ctx->blocksz) { in asd_sha_update()
[all …]
/trusted-firmware-a-latest/services/std_svc/spmd/
Dspmd_pm.c66 spmd_spm_core_context_t *ctx = spmd_get_context(); in spmd_cpu_on_finish_handler() local
72 assert(ctx != NULL); in spmd_cpu_on_finish_handler()
73 assert(ctx->state != SPMC_STATE_ON); in spmd_cpu_on_finish_handler()
90 el3_state = get_el3state_ctx(&ctx->cpu_ctx); in spmd_cpu_on_finish_handler()
97 ctx->state = SPMC_STATE_ON_PENDING; in spmd_cpu_on_finish_handler()
99 rc = spmd_spm_core_sync_entry(ctx); in spmd_cpu_on_finish_handler()
103 ctx->state = SPMC_STATE_OFF; in spmd_cpu_on_finish_handler()
107 ctx->state = SPMC_STATE_ON; in spmd_cpu_on_finish_handler()
117 spmd_spm_core_context_t *ctx = spmd_get_context(); in spmd_cpu_off_handler() local
121 assert(ctx != NULL); in spmd_cpu_off_handler()
[all …]
/trusted-firmware-a-latest/lib/cpus/aarch64/
Dcpuamu.c32 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; in cpuamu_context_save() local
38 ctx->mask = cpuamu_read_cpuamcntenset_el0(); in cpuamu_context_save()
41 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_save()
46 ctx->cnts[i] = cpuamu_cnt_read(i); in cpuamu_context_save()
51 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; in cpuamu_context_restore() local
60 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_restore()
65 cpuamu_cnt_write(i, ctx->cnts[i]); in cpuamu_context_restore()
69 cpuamu_write_cpuamcntenset_el0(ctx->mask); in cpuamu_context_restore()
/trusted-firmware-a-latest/lib/el3_runtime/aarch32/
Dcontext_mgmt.c58 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) in cm_setup_context() argument
64 assert(ctx != NULL); in cm_setup_context()
69 zeromem(ctx, sizeof(*ctx)); in cm_setup_context()
71 reg_ctx = get_regs_ctx(ctx); in cm_setup_context()
166 cpu_context_t *ctx; in cm_init_context_by_index() local
167 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); in cm_init_context_by_index()
168 cm_setup_context(ctx, ep); in cm_init_context_by_index()
178 cpu_context_t *ctx; in cm_init_my_context() local
179 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); in cm_init_my_context()
180 cm_setup_context(ctx, ep); in cm_init_my_context()
[all …]
/trusted-firmware-a-latest/services/spd/trusty/
Dtrusty.c94 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); in trusty_context_switch() local
97 assert(ctx->saved_security_state != security_state); in trusty_context_switch()
125 ctx->saved_security_state = security_state; in trusty_context_switch()
126 ret_args = trusty_context_switch_helper(&ctx->saved_sp, &args); in trusty_context_switch()
128 assert(ctx->saved_security_state == ((security_state == 0U) ? 1U : 0U)); in trusty_context_switch()
145 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); in trusty_fiq_handler() local
154 if (ctx->fiq_handler_active != 0) { in trusty_fiq_handler()
159 ctx->fiq_handler_active = 1; in trusty_fiq_handler()
160 (void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs)); in trusty_fiq_handler()
161 ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3); in trusty_fiq_handler()
[all …]
/trusted-firmware-a-latest/include/drivers/amlogic/crypto/
Dsha_dma.h26 static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) in asd_sha_init() argument
28 ctx->started = 0; in asd_sha_init()
29 ctx->mode = mode; in asd_sha_init()
30 ctx->blocksz = 0; in asd_sha_init()
33 void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len);
34 void asd_sha_finalize(struct asd_ctx *ctx);
/trusted-firmware-a-latest/services/std_svc/drtm/
Ddrtm_remediation.c17 uint64_t drtm_set_error(uint64_t x1, void *ctx) in drtm_set_error() argument
24 SMC_RET1(ctx, INTERNAL_ERROR); in drtm_set_error()
27 SMC_RET1(ctx, SUCCESS); in drtm_set_error()
30 uint64_t drtm_get_error(void *ctx) in drtm_get_error() argument
38 SMC_RET1(ctx, INTERNAL_ERROR); in drtm_get_error()
41 SMC_RET2(ctx, SUCCESS, error_code); in drtm_get_error()
/trusted-firmware-a-latest/services/std_svc/spm/spm_mm/
Dspm_mm_main.c89 static uint64_t spm_sp_synchronous_entry(sp_context_t *ctx) in spm_sp_synchronous_entry() argument
93 assert(ctx != NULL); in spm_sp_synchronous_entry()
96 cm_set_context(&(ctx->cpu_ctx), SECURE); in spm_sp_synchronous_entry()
107 rc = spm_secure_partition_enter(&ctx->c_rt_ctx); in spm_sp_synchronous_entry()
121 sp_context_t *ctx = &sp_ctx; in spm_sp_synchronous_exit() local
128 spm_secure_partition_exit(ctx->c_rt_ctx, rc); in spm_sp_synchronous_exit()
139 sp_context_t *ctx; in spm_init() local
143 ctx = &sp_ctx; in spm_init()
145 ctx->state = SP_STATE_RESET; in spm_init()
147 rc = spm_sp_synchronous_entry(ctx); in spm_init()
[all …]
Dspm_mm_setup.c29 cpu_context_t *ctx = &(sp_ctx->cpu_ctx); in spm_sp_setup() local
67 cm_setup_context(ctx, &ep_info); in spm_sp_setup()
74 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, in spm_sp_setup()
125 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1, in spm_sp_setup()
128 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1, in spm_sp_setup()
131 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1, in spm_sp_setup()
135 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
171 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); in spm_sp_setup()
179 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1, in spm_sp_setup()
182 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, in spm_sp_setup()
[all …]
/trusted-firmware-a-latest/lib/extensions/amu/aarch64/
Damu.c72 static inline __unused void ctx_write_scr_el3_amvoffen(cpu_context_t *ctx, uint64_t amvoffen) in ctx_write_scr_el3_amvoffen() argument
74 uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); in ctx_write_scr_el3_amvoffen()
79 write_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3, value); in ctx_write_scr_el3_amvoffen()
181 void amu_enable(cpu_context_t *ctx) in amu_enable() argument
189 ctx_write_scr_el3_amvoffen(ctx, 1U); in amu_enable()
416 struct amu_ctx *ctx; in amu_context_save() local
432 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
449 ctx->group0_enable = read_amcntenset0_el0_px(); in amu_context_save()
450 write_amcntenclr0_el0_px(ctx->group0_enable); in amu_context_save()
454 ctx->group1_enable = read_amcntenset1_el0_px(); in amu_context_save()
[all …]
/trusted-firmware-a-latest/services/std_svc/rmmd/
Drmmd_main.c98 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; in rmmd_rmm_sync_exit() local
101 assert(cm_get_context(REALM) == &(ctx->cpu_ctx)); in rmmd_rmm_sync_exit()
108 rmmd_rmm_exit(ctx->c_rt_ctx, rc); in rmmd_rmm_sync_exit()
123 static void manage_extensions_realm(cpu_context_t *ctx) in manage_extensions_realm() argument
125 pmuv3_enable(ctx); in manage_extensions_realm()
131 sme_enable(ctx); in manage_extensions_realm()
167 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; in rmm_init() local
172 manage_extensions_realm(&ctx->cpu_ctx); in rmm_init()
177 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); in rmm_init()
179 rc = rmmd_rmm_sync_entry(ctx); in rmm_init()
[all …]
/trusted-firmware-a-latest/plat/imx/common/
Dplat_imx8_gic.c100 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx) in plat_gic_save() argument
104 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); in plat_gic_save()
105 gicv3_distif_save(&ctx->dist_ctx); in plat_gic_save()
108 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx) in plat_gic_restore() argument
111 gicv3_distif_init_restore(&ctx->dist_ctx); in plat_gic_restore()
113 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); in plat_gic_restore()
/trusted-firmware-a-latest/include/lib/el3_runtime/aarch64/
Dcontext.h430 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) argument
431 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ argument
514 #define set_aapcs_args0(ctx, x0) do { \ argument
515 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
517 #define set_aapcs_args1(ctx, x0, x1) do { \ argument
518 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
519 set_aapcs_args0(ctx, x0); \
521 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ argument
522 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
523 set_aapcs_args1(ctx, x0, x1); \
[all …]
/trusted-firmware-a-latest/include/drivers/st/
Dstm32_saes.h49 int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt,
52 int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
54 int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
56 int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
58 int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len);
/trusted-firmware-a-latest/lib/extensions/amu/aarch32/
Damu.c270 struct amu_ctx *ctx; in amu_context_save() local
284 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
297 ctx->group0_enable = read_amcntenset0_px(); in amu_context_save()
298 write_amcntenclr0_px(ctx->group0_enable); in amu_context_save()
302 ctx->group1_enable = read_amcntenset1_px(); in amu_context_save()
303 write_amcntenclr1_px(ctx->group1_enable); in amu_context_save()
314 ctx->group0_cnts[i] = amu_group0_cnt_read(i); in amu_context_save()
319 ctx->group1_cnts[i] = amu_group1_cnt_read(i); in amu_context_save()
331 struct amu_ctx *ctx; in amu_context_restore() local
345 ctx = &amu_ctxs_[core_pos]; in amu_context_restore()
[all …]

1234