| /trusted-firmware-a-latest/fdts/ |
| D | cot_descriptors.dtsi | 18 antirollback-counter = <&trusted_nv_counter>;
37 antirollback-counter = <&trusted_nv_counter>;
51 antirollback-counter = <&trusted_nv_counter>;
62 antirollback-counter = <&trusted_nv_counter>;
73 antirollback-counter = <&trusted_nv_counter>;
83 antirollback-counter = <&trusted_nv_counter>;
97 antirollback-counter = <&trusted_nv_counter>;
108 antirollback-counter = <&trusted_nv_counter>;
128 antirollback-counter = <&non_trusted_nv_counter>;
139 antirollback-counter = <&non_trusted_nv_counter>;
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| D | stm32mp1-cot-descriptors.dtsi | 18 antirollback-counter = <&trusted_nv_counter>;
32 antirollback-counter = <&trusted_nv_counter>;
46 antirollback-counter = <&trusted_nv_counter>;
57 antirollback-counter = <&trusted_nv_counter>;
77 antirollback-counter = <&non_trusted_nv_counter>;
88 antirollback-counter = <&non_trusted_nv_counter>;
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| D | tc.dts | 86 mpmm_gear0: counter@0 {
92 mpmm_gear1: counter@1 {
98 mpmm_gear2: counter@2 {
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| /trusted-firmware-a-latest/docs/components/fconf/ |
| D | amu-bindings.rst | 37 An ``amu`` node describes the layout and meaning of the auxiliary counter
53 ``/cpus/amus/amu*/counter*`` node properties
56 A ``counter`` node describes an auxiliary counter belonging to the parent |AMU|
62 | ``reg`` | R | array | Represents the counter register |
66 | | | | indicates that this counter should |
87 counterX: counter@0 {
93 counterY: counter@1 {
104 counterZ: counter@0 {
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| /trusted-firmware-a-latest/drivers/st/clk/ |
| D | stm32mp_clkfunc.c | 327 static void stgen_set_counter(unsigned long long counter) in stgen_set_counter() argument
330 mmio_write_64(STGEN_BASE + CNTCV_OFF, counter); in stgen_set_counter()
332 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); in stgen_set_counter()
333 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); in stgen_set_counter()
344 unsigned long long counter; in stm32mp_stgen_config() local
353 counter = stm32mp_stgen_get_counter() * rate / cntfid0; in stm32mp_stgen_config()
355 stgen_set_counter(counter); in stm32mp_stgen_config()
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| /trusted-firmware-a-latest/drivers/mentor/i2c/ |
| D | mi2cv.c | 490 uint32_t counter = 0; in i2c_read() local
499 counter); in i2c_read()
505 if (counter > 0) in i2c_read()
507 counter++; in i2c_read()
538 } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); in i2c_read()
540 if (counter == I2C_MAX_RETRY_CNT) { in i2c_read()
569 uint32_t counter = 0; in i2c_write() local
578 if (counter > 0) in i2c_write()
580 counter++; in i2c_write()
604 } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); in i2c_write()
[all …]
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| /trusted-firmware-a-latest/docs/components/ |
| D | cot-binding.rst | 81 - antirollback-counter
86 counter and it is an optional property.
89 counter sub-node present in 'non-volatile counters' node.
139 antirollback-counter = <&trusted_nv_counter>;
153 antirollback-counter = <&trusted_nv_counter>;
245 non-volatile counter node binding definition
258 Definition: must be "arm, non-volatile-counter"
268 of non-volatile counter register
283 Usage: Required for every nv-counter with unique id.
290 Register base address of non-volatile counter and it is required
[all …]
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| D | firmware-update.rst | 73 The second stage Bootloader (BL2) avoids upgrading the platform NV-counter until
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| D | xlat-tables-lib-v2-design.rst | 406 A counter-example is the initialization of translation tables. In this case,
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| /trusted-firmware-a-latest/lib/extensions/amu/ |
| D | amu.mk | 14 …$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENA…
20 …r AMU FCONF support (`ENABLE_AMU_FCONF`) is not necessary when auxiliary counter support (`ENABLE_…
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| /trusted-firmware-a-latest/docs/perf/ |
| D | performance-monitoring-unit.rst | 7 This document gives an overview of the PMU counter configuration to assist with
22 - A dedicated cycle counter: ``PMCCNTR``.
46 Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
47 configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
119 - Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
121 In other words, the counter will not increment at any privilege level or
127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.
134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
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| D | psci-performance-methodology.rst | 35 (unquantified) overhead on the results. PMF uses the generic counter for
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| D | psci-performance-instr.rst | 103 implementation to be calculated, given the frequency counter.
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| D | psci-performance-juno.rst | 29 (unquantified) overhead on the results. PMF uses the generic counter for
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| /trusted-firmware-a-latest/tools/cert_create/src/ |
| D | ext.c | 243 ASN1_INTEGER *counter; in ext_new_nvcounter() local
248 counter = ASN1_INTEGER_new(); in ext_new_nvcounter()
249 ASN1_INTEGER_set(counter, value); in ext_new_nvcounter()
250 sz = i2d_ASN1_INTEGER(counter, &p); in ext_new_nvcounter()
257 ASN1_INTEGER_free(counter); in ext_new_nvcounter()
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| /trusted-firmware-a-latest/lib/mpmm/ |
| D | mpmm.mk | 16 …$(error MPMM support (`ENABLE_MPM`) requires auxiliary AMU counter support (`ENABLE_AMU_AUXILIARY_…
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| /trusted-firmware-a-latest/docs/process/ |
| D | security-hardening.rst | 85 - ``SCCD`` for the cycle counter.
92 - Prohibit general event counters and the cycle counter:
109 - Prohibit cycle counter: ``MDCR_EL3.SPME == 0 && PMCR_EL0.DP == 1``.
115 - Prohibit cycle counter: ``MDCR_EL3.SCCD == 1``
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-5.rst | 32 bit is set to zero, the cycle counter (when enabled) counts during secure world
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| D | security-advisory-tfv-10.rst | 118 3. Retrieving the security counter value from an X.509 certificate to protect
131 - The platform uses a custom chain of trust which uses the non-volatile counter
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| /trusted-firmware-a-latest/docs/ |
| D | glossary.rst | 20 that exposes CPU core runtime metrics as a set of counter registers.
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| D | porting-guide.rst | 844 non-volatile counter value stored in the platform in the second argument. The
845 cookie in the first argument may be used to select the counter in case the
850 The function returns 0 on success. Any other value means the counter value could
862 counter value in the platform. The cookie in the first argument may be used to
863 select the counter (as explained in plat_get_nv_ctr()). The second argument is
864 the updated counter value to be written to the NV counter.
866 The function returns 0 on success. Any other value means the counter value could
882 descriptor and may be used to decide if the counter is allowed to be
883 updated or not. The third argument is the updated counter value to
884 be written to the NV counter.
[all …]
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| /trusted-firmware-a-latest/docs/design_documents/ |
| D | rss.rst | 139 increase a non-volatile counter. Please refer to the
652 - ``Non-volatile counter for CCA firmware (BL2, BL31, RMM).``
653 - ``Non-volatile counter for secure firmware.``
654 - ``Non-volatile counter for non-secure firmware.``
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| /trusted-firmware-a-latest/docs/plat/st/ |
| D | stm32mp1.rst | 97 - | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
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| /trusted-firmware-a-latest/docs/threat_model/ |
| D | threat_model.rst | 723 | | corresponding NV counter stored in hardware to |
724 | | make sure the new counter value is larger than |
725 | | the current counter value. |
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| /trusted-firmware-a-latest/docs/design/ |
| D | auth-framework.rst | 185 NV counter, then the value of the counter to compare with can only be
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