| /trusted-firmware-a-latest/services/std_svc/spm/spm_mm/ |
| D | spm_mm_xlat.c | 31 static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) in smc_attr_to_mmap_attr() argument
35 unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) in smc_attr_to_mmap_attr()
49 if ((attributes & MM_SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { in smc_attr_to_mmap_attr()
93 uint32_t attributes; in spm_memory_attributes_get_smc_handler() local
98 base_va, &attributes); in spm_memory_attributes_get_smc_handler()
106 return (int32_t) smc_mmap_to_smc_attr(attributes); in spm_memory_attributes_get_smc_handler()
119 uint32_t attributes = (uint32_t) smc_attributes; in spm_memory_attributes_set_smc_handler() local
123 INFO(" Attributes : 0x%x\n", attributes); in spm_memory_attributes_set_smc_handler()
129 smc_attr_to_mmap_attr(attributes)); in spm_memory_attributes_set_smc_handler()
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| /trusted-firmware-a-latest/drivers/scmi-msg/ |
| D | power_domain.h | 31 uint32_t attributes; member
41 uint32_t attributes; member
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| D | common.h | 50 uint32_t attributes; member
61 uint32_t attributes; member
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| D | clock.h | 43 uint32_t attributes; member
103 uint32_t attributes; member
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| D | power_domain.c | 90 return_values.attributes = plat_scmi_pd_count(msg->agent_id); in report_attributes()
107 .attributes = 0U, in report_message_attributes()
152 return_values.attributes = plat_scmi_pd_get_attributes(msg->agent_id, pd_id); in scmi_pd_attributes()
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| D | clock.c | 99 .attributes = SCMI_CLOCK_PROTOCOL_ATTRIBUTES(1U, agent_count), in report_attributes()
116 .attributes = 0U, in report_message_attributes()
162 return_values.attributes = plat_scmi_clock_get_state(msg->agent_id, in scmi_clock_attributes()
243 enable = in_args->attributes & SCMI_CLOCK_CONFIG_SET_ENABLE_MASK; in scmi_clock_config_set()
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| D | reset_domain.h | 44 uint32_t attributes; member
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| D | base.c | 39 .attributes = SCMI_BASE_PROTOCOL_ATTRIBUTES(protocol_count, 0U), in report_attributes()
56 .attributes = 0U, in report_message_attributes()
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| D | reset_domain.c | 67 .attributes = plat_scmi_rstd_count(msg->agent_id), in report_attributes()
84 .attributes = 0U, in report_message_attributes()
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| /trusted-firmware-a-latest/lib/xlat_tables_v2/ |
| D | xlat_tables_utils.c | 346 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry, in xlat_get_mem_attributes_internal() argument
396 assert(attributes != NULL); in xlat_get_mem_attributes_internal()
397 *attributes = 0U; in xlat_get_mem_attributes_internal()
402 *attributes |= MT_MEMORY; in xlat_get_mem_attributes_internal()
404 *attributes |= MT_NON_CACHEABLE; in xlat_get_mem_attributes_internal()
407 *attributes |= MT_DEVICE; in xlat_get_mem_attributes_internal()
413 *attributes |= MT_RW; in xlat_get_mem_attributes_internal()
419 *attributes |= MT_USER; in xlat_get_mem_attributes_internal()
425 *attributes |= MT_NS; in xlat_get_mem_attributes_internal()
430 *attributes |= MT_EXECUTE_NEVER; in xlat_get_mem_attributes_internal()
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| /trusted-firmware-a-latest/bl32/tsp/ |
| D | ffa_helpers.c | 60 ffa_mem_attr16_t attributes, ffa_mtd_flag32_t flags, in ffa_memory_region_init_header() argument
72 memory_region->memory_region_attributes = attributes; in ffa_memory_region_init_header()
99 ffa_mem_attr16_t attributes) in ffa_memory_retrieve_request_init() argument
101 ffa_memory_region_init_header(memory_region, sender, attributes, flags, in ffa_memory_retrieve_request_init()
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| /trusted-firmware-a-latest/docs/components/ |
| D | secure-partition-manager-mm.rst | 293 partition (e.g. management of memory attributes in the translation tables for
402 that it needs access to and their attributes. The SPM validates this resource
405 1. Device regions are mapped with nGnRE attributes and Execute Never
419 attributes.
485 memory attributes described earlier.
557 memory attributes described earlier.
602 the Secure EL1&0 Translation regime with appropriate memory attributes.
604 attributes used in the Translation tables. The definitions of these attributes
619 executable file and their permission attributes (e.g. read-write data, read-only
629 attributes.
[all …]
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| D | ffa-manifest-binding.rst | 191 - attributes [mandatory]
228 - attributes [mandatory]
260 - A list of (id, attributes) pair describing the device interrupts, where:
263 - attributes: A <u32> value, containing attributes for each interrupt ID:
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| D | xlat-tables-lib-v2-design.rst | 26 #. Support for changing memory attributes of memory regions at run-time.
68 - its attributes;
77 The region attributes specify the type of memory (for example device or cached
80 the EL1&0 translation regime, the attributes also specify whether the region is
96 with different memory attributes, the library might need to split the existing
318 translation tables and helpers to query memory attributes and to modify them.
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| D | granule-protection-tables-design.rst | 92 its attributes that can be used by the GPT library to initialize the tables.
98 #. The desired attributes of this memory region (mapping type, PAS type)
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| D | rmm-el3-comms-spec.rst | 107 Normal memory attributes (IWB-OWB-ISH) at EL3. At boot, this memory will be
121 memory attributes.
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| D | sdei.rst | 57 available on the platform, along with their attributes.
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| /trusted-firmware-a-latest/plat/arm/board/fvp/fdts/ |
| D | optee_sp_manifest.dts | 41 attributes = <0x3>; /* read-write */
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| /trusted-firmware-a-latest/docs/plat/ |
| D | imx8m.rst | 84 platform is mapped into the EL3 with MT_RW attributes.
102 Therefore, DRAM mapping is done with MT_RW attributes, as it is required for
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| /trusted-firmware-a-latest/plat/nvidia/tegra/scat/ |
| D | bl31.scat | 245 * memory attributes for the coherent data page tables.
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-3.rst | 28 has memory attributes represented by the ``mmap_attr_t`` enumeration type. This
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| /trusted-firmware-a-latest/docs/design/ |
| D | psci-pd-tree.rst | 36 #. The attributes of a core power domain differ from the attributes of power
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| D | firmware-design.rst | 665 uint32_t attr; /* attributes: unused bits SBZ */
1336 element of the array specifies the interrupt number and its attributes
1671 memory regions to set the right memory attributes. When
2140 shareability, cacheability and memory attributes is accessed by multiple CPUs
2145 TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2150 mismatched attributes from various CPUs are allocated in a coherent memory
2153 the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
2155 due to mismatched memory attributes.
2160 work around the issue of mismatched memory attributes by performing software
2227 and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
[all …]
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| /trusted-firmware-a-latest/docs/design_documents/ |
| D | drtm_poc.rst | 37 system’s state, measures security-critical attributes of the system,
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| /trusted-firmware-a-latest/docs/process/ |
| D | coding-style.rst | 252 Place any function attributes after the function type and before the function
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