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Searched refs:arg1 (Results 1 – 25 of 166) sorted by relevance

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/trusted-firmware-a-latest/plat/mediatek/drivers/dfd/
Ddfd.c13 static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, in dfd_smc_dispatcher() argument
22 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
26 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
27 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
32 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a-latest/plat/arm/board/juno/
Djuno_bl31_setup.c16 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
20 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
23 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
27 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
/trusted-firmware-a-latest/plat/xilinx/common/include/
Dpm_api_sys.h57 uint32_t arg1, uint32_t arg2, uint32_t arg3,
59 enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
78 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ argument
79 pl[1] = (uint32_t)(arg1); \
83 #define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ argument
85 PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \
88 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
90 PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
93 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
95 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
[all …]
/trusted-firmware-a-latest/services/arm_arch_svc/
Darm_arch_svc_setup.c23 static int32_t smccc_arch_features(u_register_t arg1) in smccc_arch_features() argument
25 switch (arg1) { in smccc_arch_features()
30 return plat_is_smccc_feature_available(arg1); in smccc_arch_features()
104 static int32_t smccc_arch_id(u_register_t arg1) in smccc_arch_id() argument
106 if (arg1 == SMCCC_GET_SOC_REVISION) { in smccc_arch_id()
109 if (arg1 == SMCCC_GET_SOC_VERSION) { in smccc_arch_id()
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dfd/
Dplat_dfd.c70 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
78 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
82 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
83 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
88 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
89 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/dfd/
Dplat_dfd.c112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
119 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
123 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
129 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a-latest/bl32/tsp/
Dtsp_private.h52 uint64_t arg1,
60 uint64_t arg1,
68 uint64_t arg1,
77 uint64_t arg1,
107 uint64_t arg1,
116 uint64_t arg1,
125 uint64_t arg1,
134 uint64_t arg1,
Dtsp_common.c35 uint64_t arg1, in set_smc_args() argument
53 write_sp_arg(pcpu_smc_args, SMC_ARG1, arg1); in set_smc_args()
89 uint64_t arg1, in tsp_system_off_main() argument
117 uint64_t arg1, in tsp_system_reset_main() argument
147 uint64_t arg1, in tsp_abort_smc_handler() argument
Dtsp_ffa_main.c83 uint64_t arg1, in ffa_test_relay() argument
280 uint64_t arg1, in tsp_cpu_off_main() argument
318 uint64_t arg1, in tsp_cpu_suspend_main() argument
355 uint64_t arg1, in tsp_cpu_resume_main() argument
388 uint64_t arg1, in handle_framework_message() argument
397 if (ffa_endpoint_source(arg1) != spmc_id) { in handle_framework_message()
405 return tsp_cpu_off_main(arg0, arg1, arg2, arg3, in handle_framework_message()
408 return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3, in handle_framework_message()
414 return tsp_cpu_resume_main(arg0, arg1, arg2, arg3, in handle_framework_message()
428 uint64_t arg1, in handle_partition_message() argument
[all …]
/trusted-firmware-a-latest/plat/arm/board/fvp/sp_min/
Dfvp_sp_min_setup.c17 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
27 INFO("SP_MIN FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in plat_arm_sp_min_early_platform_setup()
29 fconf_populate("FW_CONFIG", arg1); in plat_arm_sp_min_early_platform_setup()
33 arg1 = tos_fw_config_info->config_addr; in plat_arm_sp_min_early_platform_setup()
37 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dpm_api_ioctl.c603 uint32_t arg1, in pm_api_ioctl() argument
615 ret = pm_ioctl_set_rpu_oper_mode(arg1); in pm_api_ioctl()
618 ret = pm_ioctl_config_boot_addr(nid, arg1); in pm_api_ioctl()
621 ret = pm_ioctl_config_tcm_comb(arg1); in pm_api_ioctl()
624 ret = pm_ioctl_set_tapdelay_bypass(arg1, arg2); in pm_api_ioctl()
627 ret = pm_ioctl_sd_dll_reset(nid, arg1); in pm_api_ioctl()
630 ret = pm_ioctl_sd_set_tapdelay(nid, arg1, arg2); in pm_api_ioctl()
633 ret = pm_ioctl_set_pll_frac_mode(arg1, arg2); in pm_api_ioctl()
636 ret = pm_ioctl_get_pll_frac_mode(arg1, value); in pm_api_ioctl()
639 ret = pm_ioctl_set_pll_frac_data(arg1, arg2); in pm_api_ioctl()
[all …]
Dzynqmp_pm_api_sys.h45 #define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \ argument
46 pl[1] = (uint32_t)(arg1); \
50 #define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \ argument
52 PM_PACK_PAYLOAD2(pl, arg0, arg1); \
55 #define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \ argument
57 PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \
60 #define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \
65 #define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
67 PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dfd/
Dplat_dfd.c128 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
136 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
140 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
141 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
146 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
147 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
/trusted-firmware-a-latest/plat/arm/board/fvp/
Dfvp_bl31_setup.c23 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
31 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
33 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
37 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
52 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
Dfvp_bl2_setup.c24 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
26 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
76 param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; in plat_get_next_bl_params()
87 param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE | in plat_get_next_bl_params()
97 param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr; in plat_get_next_bl_params()
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/drivers/mce/
Dmce.c158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler() argument
177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
191 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, in mce_command_handler()
201 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); in mce_command_handler()
215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler()
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
296 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler()
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
[all …]
/trusted-firmware-a-latest/drivers/arm/css/scmi/
Dscmi_private.h97 #define SCMI_PAYLOAD_ARG1(payld_arr, arg1) \ argument
98 mmio_write_32((uintptr_t)&payld_arr[0], arg1)
100 #define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ argument
101 SCMI_PAYLOAD_ARG1(payld_arr, arg1); \
105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument
106 SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \
/trusted-firmware-a-latest/bl2/
Dbl2_main.c41 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_el3_setup() argument
45 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_el3_setup()
63 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_setup() argument
67 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_setup()
/trusted-firmware-a-latest/plat/arm/board/fvp_ve/sp_min/
Dfvp_ve_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
/trusted-firmware-a-latest/plat/arm/board/corstone700/sp_min/
Dcorstone700_sp_min_setup.c9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
/trusted-firmware-a-latest/plat/arm/board/a5ds/sp_min/
Da5ds_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
/trusted-firmware-a-latest/plat/arm/common/sp_min/
Darm_sp_min_setup.c97 bl33_image_ep_info.args.arg1 = ~0U; in arm_sp_min_early_platform_setup()
136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
/trusted-firmware-a-latest/plat/arm/board/a5ds/
Da5ds_bl2_setup.c9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
/trusted-firmware-a-latest/include/bl2/
Dbl2.h12 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
14 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
/trusted-firmware-a-latest/plat/arm/board/fvp_ve/
Dfvp_ve_bl2_setup.c16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()

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