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/trusted-firmware-a-latest/plat/arm/board/corstone700/common/drivers/mhu/
Dcorstone700_mhu.c30 void mhu_secure_message_start(uintptr_t address, unsigned int slot_id) in mhu_secure_message_start() argument
47 intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_start()
62 void mhu_secure_message_send(uintptr_t address, in mhu_secure_message_send() argument
71 assert((mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_send()
74 MHU_V2_ACCESS_REQUEST(address); in mhu_secure_message_send()
79 access_ready = MHU_V2_IS_ACCESS_READY(address); in mhu_secure_message_send()
91 mmio_write_32(address + CPU_INTR_S_SET, message); in mhu_secure_message_send()
94 void mhu_secure_message_end(uintptr_t address, unsigned int slot_id) in mhu_secure_message_end() argument
101 MHU_V2_CLEAR_REQUEST(address); in mhu_secure_message_end()
Dcorstone700_mhu.h30 void mhu_secure_message_start(uintptr_t address, unsigned int slot_id);
31 void mhu_secure_message_send(uintptr_t address,
34 void mhu_secure_message_end(uintptr_t address, unsigned int slot_id);
/trusted-firmware-a-latest/plat/st/common/
Dstm32cubeprogrammer_usb.c23 uintptr_t address; member
41 dfu->address = UNDEFINED_DOWN_ADDR; \
66 dfu->buffer[1] = (uint8_t)(dfu->address); in dfu_callback_upload()
67 dfu->buffer[2] = (uint8_t)(dfu->address >> 8); in dfu_callback_upload()
68 dfu->buffer[3] = (uint8_t)(dfu->address >> 16); in dfu_callback_upload()
69 dfu->buffer[4] = (uint8_t)(dfu->address >> 24); in dfu_callback_upload()
76 dfu->address == UNDEFINED_DOWN_ADDR) { in dfu_callback_upload()
109 (dfu->address == UNDEFINED_DOWN_ADDR)) { in dfu_callback_download()
111 dfu->phase, alt, (uint32_t)dfu->address); in dfu_callback_download()
115 VERBOSE("Download %d %lx %x\n", alt, dfu->address, *len); in dfu_callback_download()
[all …]
/trusted-firmware-a-latest/plat/arm/board/fvp/fdts/
Dfvp_fw_config.dts16 load-address = <0x0 0x4001300>;
22 load-address = <0x0 0x07f00000>;
25 secondary-load-address = <0x0 0x82000000>;
35 load-address = <0x0 0x04001300>;
44 load-address = <0x0 0x04001500>;
46 secondary-load-address = <0x0 0x7e00000>;
54 load-address = <0x0 0x80000000>;
/trusted-firmware-a-latest/plat/rpi/rpi4/
Drpi4_pci_svc.c46 static uint64_t pci_segment_lib_get_base(uint32_t address, uint32_t offset) in pci_segment_lib_get_base() argument
57 if (address != 0U) { in pci_segment_lib_get_base()
66 bus = PCI_ADDR_BUS(address); in pci_segment_lib_get_base()
67 dev = PCI_ADDR_DEV(address); in pci_segment_lib_get_base()
68 fun = PCI_ADDR_FUN(address); in pci_segment_lib_get_base()
69 address = (bus << PCIE_EXT_BUS_SHIFT) | in pci_segment_lib_get_base()
85 mmio_write_32(PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, address); in pci_segment_lib_get_base()
/trusted-firmware-a-latest/plat/arm/board/tc/fdts/
Dtc_tb_fw_config.dts38 load-address = <0xfee00000>;
42 load-address = <0xfec00000>;
48 load-address = <0xfd280000>;
53 load-address = <0xfe000000>;
59 load-address = <0xfe100000>;
65 load-address = <0xfe200000>;
70 load-address = <0xfe600000>;
Dtc_fw_config.dts16 load-address = <0x0 0x4001300>;
22 load-address = <0x0 0x04001700>;
28 load-address = <0x0 0x83000000>;
/trusted-firmware-a-latest/docs/components/fconf/
Dfconf_properties.rst21 - load-address [mandatory]
23 - Physical loading base address of the configuration.
24 If secondary-load-address is also provided (see below), then this is the
25 primary load address.
35 - secondary-load-address [optional]
37 - A platform uses this physical address to copy the configuration to
/trusted-firmware-a-latest/docs/plat/marvell/armada/misc/
Dmvebu-ccu.rst1 Marvell CCU address decoding bindings
4 CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The CCU node includes a description of the address decoding configuration.
22 - Base address of the window
Dmvebu-amb.rst1 AMB - AXI MBUS address decoding
6 The Runit offers a second level of address windows lookup. It is used to map
10 address space and the properties associated with that address space.
48 - Base address of the window
Dmvebu-io-win.rst1 Marvell IO WIN address decoding bindings
4 IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The IO WIN includes a description of the address decoding configuration.
9 layer of decoding. This additional address decoding layer defines one of the
33 - Base address of the window
Dmvebu-iob.rst1 Marvell IOB address decoding bindings
4 IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The IOB includes a description of the address decoding configuration.
9 When a transaction passes through the IOB, its address is compared to each of
26 - Base address of the window
/trusted-firmware-a-latest/plat/arm/board/morello/fdts/
Dmorello_fw_config.dts15 load-address = <0x0 0x4001300>;
21 load-address = <0x0 0xFEF00000>;
27 load-address = <0x0 0xFEFF8000>;
/trusted-firmware-a-latest/plat/arm/board/n1sdp/fdts/
Dn1sdp_fw_config.dts14 load-address = <0x0 0x4001300>;
19 load-address = <0x0 0x4001600>;
24 load-address = <0x0 0xFEF00000>;
/trusted-firmware-a-latest/docs/plat/
Dxilinx-zynqmp.rst34 - ``XILINX_OF_BOARD_DTB_ADDR`` : Specifies the base address of Device tree.
35 - ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
37 - ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
54 To reserve the above memory range in device tree, the device tree base address
58 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
60 The default DTB base address for ZynqMP platform is 0x100000. This default value
61 is not set in the code and to use this default address, user still needs to
65 the DDR address location using the build time parameters ZYNQMP_ATF_MEM_BASE and
68 The DDR address must be reserved in the DTB by the user, either by manually
69 adding the reserved memory node, in the device tree, with the required address
[all …]
/trusted-firmware-a-latest/fdts/
Dstm32mp15-fw-config.dtsi35 load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
41 load-address = <0x0 STM32MP_BL33_BASE>;
48 load-address = <0x0 STM32MP_OPTEE_BASE>;
54 load-address = <0x0 STM32MP_BL32_BASE>;
60 load-address = <0x0 STM32MP_BL32_DTB_BASE>;
Dstm32mp13-fw-config.dtsi27 load-address = <0x0 STM32MP_HW_CONFIG_BASE>;
33 load-address = <0x0 STM32MP_BL33_BASE>;
39 load-address = <0x0 DDR_SEC_BASE>;
/trusted-firmware-a-latest/docs/design/
Dreset-design.rst30 address" for more information.
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
36 Therefore, all CPUs start at the same address (typically address 0) whenever
40 If the reset vector address (reflected in the reset vector base address register
42 at the right address, both on a cold and warm reset. Therefore, the boot type
45 |Reset code flow with programmable reset address|
51 On both the FVP and Juno platforms, the reset vector address is not programmable
77 Programmable CPU reset address, Cold boot on a single CPU
81 a programmable CPU reset address and which release a single CPU out of reset.
[all …]
/trusted-firmware-a-latest/plat/marvell/armada/common/
Dmarvell_pm.c24 void marvell_program_mailbox(uintptr_t address) in marvell_program_mailbox() argument
37 mailbox[MBOX_IDX_SEC_ADDR] = address; in marvell_program_mailbox()
/trusted-firmware-a-latest/common/backtrace/
Dbacktrace.c40 static inline uintptr_t extract_address(uintptr_t address) in extract_address() argument
42 uintptr_t ret = address; in extract_address()
62 static bool is_address_readable(uintptr_t address) in is_address_readable() argument
65 uintptr_t addr = extract_address(address); in is_address_readable()
/trusted-firmware-a-latest/plat/arm/board/juno/fdts/
Djuno_fw_config.dts16 load-address = <0x0 0x4001300>;
22 load-address = <0x0 0x82000000>;
/trusted-firmware-a-latest/plat/arm/board/rde1edge/fdts/
Drde1edge_fw_config.dts16 load-address = <0x0 0x4001300>;
22 load-address = <0x0 0xFEF00000>;
/trusted-firmware-a-latest/plat/arm/board/fvp_ve/fdts/
Dfvp_ve_fw_config.dts16 load-address = <0x0 0x80001300>;
22 load-address = <0x0 0x82000000>;
/trusted-firmware-a-latest/plat/arm/board/a5ds/fdts/
Da5ds_fw_config.dts16 load-address = <0x0 0x2001300>;
22 load-address = <0x0 0x83000000>;
/trusted-firmware-a-latest/plat/arm/board/rdn1edge/fdts/
Drdn1edge_fw_config.dts15 load-address = <0x0 0x4001300>;
21 load-address = <0x0 0xFEF00000>;

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