| /trusted-firmware-a-latest/plat/arm/board/rdv1mc/ |
| D | rdv1mc_plat.c | 59 PLAT_ARM_GICR_BASE,
61 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
64 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
68 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
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| /trusted-firmware-a-latest/services/spd/trusty/ |
| D | generic-arm64-smcall.c | 20 #define PLAT_ARM_GICR_BASE GICR_BASE macro
27 #ifndef PLAT_ARM_GICR_BASE
28 #define PLAT_ARM_GICR_BASE SMC_UNK macro
74 return PLAT_ARM_GICR_BASE; in trusty_get_reg_base()
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| /trusted-firmware-a-latest/plat/arm/board/rdn2/ |
| D | rdn2_plat.c | 69 PLAT_ARM_GICR_BASE,
72 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
76 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
80 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
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| /trusted-firmware-a-latest/plat/arm/board/rdn2/include/ |
| D | platform_def.h | 94 #define PLAT_ARM_GICR_BASE UL(0x30100000) macro
96 #define PLAT_ARM_GICR_BASE UL(0x30300000) macro
98 #define PLAT_ARM_GICR_BASE UL(0x301C0000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/rdn1edge/ |
| D | rdn1edge_plat.c | 36 PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
37 PLAT_ARM_GICR_BASE +
|
| /trusted-firmware-a-latest/plat/arm/board/n1sdp/ |
| D | n1sdp_bl31_setup.c | 61 PLAT_ARM_GICR_BASE,
62 PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET,
|
| /trusted-firmware-a-latest/plat/arm/board/rde1edge/include/ |
| D | platform_def.h | 46 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/sgi575/include/ |
| D | platform_def.h | 47 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/rdn1edge/include/ |
| D | platform_def.h | 52 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/rdv1/include/ |
| D | platform_def.h | 66 #define PLAT_ARM_GICR_BASE UL(0x30140000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/rdv1mc/include/ |
| D | platform_def.h | 61 #define PLAT_ARM_GICR_BASE UL(0x30140000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/fvp/ |
| D | fvp_gicv3.c | 125 fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; in plat_arm_gic_driver_init()
|
| /trusted-firmware-a-latest/plat/arm/common/ |
| D | arm_gicv3.c | 34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
|
| /trusted-firmware-a-latest/plat/arm/board/tc/include/ |
| D | platform_def.h | 267 #define PLAT_ARM_GICR_BASE UL(0x30080000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/fvp_r/include/ |
| D | platform_def.h | 251 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE macro
|
| /trusted-firmware-a-latest/plat/arm/board/morello/include/ |
| D | platform_def.h | 241 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
|
| /trusted-firmware-a-latest/plat/arm/board/n1sdp/include/ |
| D | platform_def.h | 275 #define PLAT_ARM_GICR_BASE 0x300C0000 macro
|
| /trusted-firmware-a-latest/plat/arm/board/fvp/include/ |
| D | platform_def.h | 398 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE macro
|
