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Searched refs:BASE_GICD_BASE (Results 1 – 25 of 29) sorted by relevance

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/trusted-firmware-a-latest/plat/mediatek/drivers/cirq/
Dmt_cirq.c37 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4), in mt_irq_mask_restore()
39 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8), in mt_irq_mask_restore()
41 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc), in mt_irq_mask_restore()
43 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10), in mt_irq_mask_restore()
45 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14), in mt_irq_mask_restore()
47 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18), in mt_irq_mask_restore()
49 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c), in mt_irq_mask_restore()
51 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20), in mt_irq_mask_restore()
53 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24), in mt_irq_mask_restore()
55 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28), in mt_irq_mask_restore()
[all …]
/trusted-firmware-a-latest/plat/arm/board/fvp/
Dfvp_def.h60 #define DEVICE1_BASE BASE_GICD_BASE
64 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
68 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
137 #define BASE_GICD_BASE UL(0x2f000000) macro
/trusted-firmware-a-latest/plat/qti/sc7180/inc/
Dplatform_def.h130 #define BASE_GICD_BASE 0x17A00000 macro
136 #define QTI_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/qti/sc7280/inc/
Dplatform_def.h130 #define BASE_GICD_BASE 0x17A00000 macro
136 #define QTI_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/xilinx/zynqmp/include/
Dplat_macros.S23 mov_imm x16, BASE_GICD_BASE
Dplatform_def.h125 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/mediatek/mt8173/
Dplat_mt_gic.c26 BASE_GICD_BASE, in plat_mt_gic_init()
/trusted-firmware-a-latest/include/plat/nuvoton/common/
Dplat_macros.S24 mov_imm x16, BASE_GICD_BASE
/trusted-firmware-a-latest/plat/nuvoton/common/
Dplat_nuvoton_gic.c20 .gicd_base = BASE_GICD_BASE,
/trusted-firmware-a-latest/plat/rockchip/rk3399/
Drk3399_def.h29 #define BASE_GICD_BASE (GIC500_BASE) macro
/trusted-firmware-a-latest/include/plat/nuvoton/npcm845x/
Dplatform_def.h146 #define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) macro
152 #define DEVICE1_BASE BASE_GICD_BASE
176 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/arm/board/fvp/include/
Dplat_macros.S33 mov_imm x16, BASE_GICD_BASE
/trusted-firmware-a-latest/plat/rockchip/rk3399/include/
Dplatform_def.h89 #define PLAT_RK_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/mediatek/mt8173/include/
Dplat_macros.S35 mov_imm x16, BASE_GICD_BASE
Dplatform_def.h118 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
Dmt8173_def.h68 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8183/include/
Dplat_macros.S35 mov_imm x26, BASE_GICD_BASE
Dplatform_def.h116 #define BASE_GICD_BASE MT_GIC_BASE macro
130 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/mediatek/mt8192/include/
Dplatform_def.h82 #define BASE_GICD_BASE MT_GIC_BASE macro
/trusted-firmware-a-latest/plat/mediatek/mt8186/include/
Dplatform_def.h83 #define BASE_GICD_BASE MT_GIC_BASE macro
/trusted-firmware-a-latest/plat/mediatek/mt8195/include/
Dplatform_def.h96 #define BASE_GICD_BASE MT_GIC_BASE macro
/trusted-firmware-a-latest/plat/mediatek/drivers/gic600/
Dmt_gic_v3.c220 val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_get_pending()
231 mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + in mt_irq_set_pending()
/trusted-firmware-a-latest/plat/mediatek/mt8188/include/
Dplatform_def.h97 #define BASE_GICD_BASE (MT_GIC_BASE) macro
/trusted-firmware-a-latest/plat/arm/board/fvp_r/include/
Dplatform_def.h250 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dpm_client.c181 uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4U; in pm_client_set_wakeup_sources()

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