Home
last modified time | relevance | path

Searched refs:ARRAY_SIZE (Results 1 – 25 of 242) sorted by relevance

12345678910

/trusted-firmware-a-latest/plat/imx/imx93/
Dtrdc.c24 unsigned int trdc_mgr_num = ARRAY_SIZE(trdc_mgr_blks);
28 trdc_a_mbc_glbac, ARRAY_SIZE(trdc_a_mbc_glbac),
29 trdc_a_mbc, ARRAY_SIZE(trdc_a_mbc),
30 trdc_a_mrc_glbac, ARRAY_SIZE(trdc_a_mrc_glbac),
31 trdc_a_mrc, ARRAY_SIZE(trdc_a_mrc)
34 trdc_w_mbc_glbac, ARRAY_SIZE(trdc_w_mbc_glbac),
35 trdc_w_mbc, ARRAY_SIZE(trdc_w_mbc),
36 trdc_w_mrc_glbac, ARRAY_SIZE(trdc_w_mrc_glbac),
37 trdc_w_mrc, ARRAY_SIZE(trdc_w_mrc)
40 trdc_n_mbc_glbac, ARRAY_SIZE(trdc_n_mbc_glbac),
[all …]
/trusted-firmware-a-latest/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/
Dmarvell_plat_config.c38 *size = ARRAY_SIZE(amb_memory_map_cp0); in marvell_get_amb_memory_map()
42 *size = ARRAY_SIZE(amb_memory_map_cp1); in marvell_get_amb_memory_map()
109 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
164 *size = ARRAY_SIZE(iob_memory_map_cp0); in marvell_get_iob_memory_map()
168 *size = ARRAY_SIZE(iob_memory_map_cp1); in marvell_get_iob_memory_map()
172 *size = ARRAY_SIZE(iob_memory_map_cp2); in marvell_get_iob_memory_map()
209 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dpm_api_clock.c834 .num_nodes = ARRAY_SIZE(ignore_unused_pll_nodes),
852 .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
860 .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
872 .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
890 .num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
902 .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
910 .num_nodes = ARRAY_SIZE(generic_pll_nodes),
928 .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
936 .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
948 .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
[all …]
/trusted-firmware-a-latest/plat/marvell/octeontx/otx2/t91/t9130/board/
Dmarvell_plat_config.c32 *size = ARRAY_SIZE(amb_memory_map_cp0); in marvell_get_amb_memory_map()
86 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
133 *size = ARRAY_SIZE(iob_memory_map_cp0); in marvell_get_iob_memory_map()
137 *size = ARRAY_SIZE(iob_memory_map_cp1); in marvell_get_iob_memory_map()
141 *size = ARRAY_SIZE(iob_memory_map_cp2); in marvell_get_iob_memory_map()
177 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0_mochabin/board/
Dmarvell_plat_config.c35 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
66 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
93 *size = ARRAY_SIZE(iob_memory_map); in marvell_get_iob_memory_map()
128 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_mcbin/board/
Dmarvell_plat_config.c67 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
102 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
142 *size = ARRAY_SIZE(iob_memory_map_cp0); in marvell_get_iob_memory_map()
146 *size = ARRAY_SIZE(iob_memory_map_cp1); in marvell_get_iob_memory_map()
185 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_puzzle/board/
Dmarvell_plat_config.c67 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
106 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
146 *size = ARRAY_SIZE(iob_memory_map_cp0); in marvell_get_iob_memory_map()
150 *size = ARRAY_SIZE(iob_memory_map_cp1); in marvell_get_iob_memory_map()
186 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/
Dsoc.c182 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); in soc_early_init()
187 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in soc_early_init()
280 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in plat_get_power_domain_tree_desc()
302 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in plat_ls_get_cluster_core_count()
331 ARRAY_SIZE(ls_interrupt_props), in soc_platform_setup()
344 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in soc_init()
356 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); in soc_init()
399 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_tot_num_cores()
408 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_pmu_idle_cluster_mask()
417 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_pmu_flush_cluster_mask()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0/board/
Dmarvell_plat_config.c33 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
72 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
112 *size = ARRAY_SIZE(iob_memory_map_cp0); in marvell_get_iob_memory_map()
116 *size = ARRAY_SIZE(iob_memory_map_cp1); in marvell_get_iob_memory_map()
155 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/socionext/uniphier/
Duniphier_boot_device.c82 assert(boot_sel < ARRAY_SIZE(uniphier_ld11_boot_device_table)); in uniphier_ld11_get_boot_device()
110 assert(boot_sel < ARRAY_SIZE(uniphier_pxs3_boot_device_table)); in uniphier_pxs3_get_boot_device()
146 assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); in uniphier_get_boot_device()
149 assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); in uniphier_get_boot_device()
174 assert(soc < ARRAY_SIZE(uniphier_have_onchip_scp)); in uniphier_get_boot_master()
179 assert(soc < ARRAY_SIZE(uniphier_boot_device_info)); in uniphier_get_boot_master()
Duniphier_gicv3.c64 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
73 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
82 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
91 assert(soc < ARRAY_SIZE(uniphier_gic_driver_data)); in uniphier_gic_driver_init()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0/board/
Dmarvell_plat_config.c33 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
64 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
91 *size = ARRAY_SIZE(iob_memory_map); in marvell_get_iob_memory_map()
126 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/marvell/armada/a8k/a70x0_amc/board/
Dmarvell_plat_config.c30 *size = ARRAY_SIZE(amb_memory_map); in marvell_get_amb_memory_map()
61 *size = ARRAY_SIZE(io_win_memory_map); in marvell_get_io_win_memory_map()
82 *size = ARRAY_SIZE(iob_memory_map); in marvell_get_iob_memory_map()
117 *size = ARRAY_SIZE(ccu_memory_map); in marvell_get_ccu_memory_map()
/trusted-firmware-a-latest/plat/arm/common/
Darm_nor_psci_mem_protect.c105 ARRAY_SIZE(arm_ram_ranges), in arm_nor_psci_do_dyn_mem_protect()
125 ARRAY_SIZE(arm_ram_ranges)); in arm_nor_psci_do_static_mem_protect()
136 ARRAY_SIZE(arm_ram_ranges), in arm_psci_mem_protect_chk()
Darm_ccn.c19 .num_masters = ARRAY_SIZE(master_to_rn_id_map),
23 CASSERT(PLAT_ARM_CLUSTER_COUNT == ARRAY_SIZE(master_to_rn_id_map),
/trusted-firmware-a-latest/drivers/st/pmic/
Dstpmic1.c443 .voltage_table_size = ARRAY_SIZE(buck1_voltage_table),
457 .voltage_table_size = ARRAY_SIZE(buck2_voltage_table),
471 .voltage_table_size = ARRAY_SIZE(buck3_voltage_table),
485 .voltage_table_size = ARRAY_SIZE(buck4_voltage_table),
499 .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table),
511 .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table),
523 .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table),
535 .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table),
547 .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table),
559 .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table),
[all …]
/trusted-firmware-a-latest/plat/arm/board/rde1edge/
Drde1edge_security.c19 .dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
29 .acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
/trusted-firmware-a-latest/plat/arm/board/rdn1edge/
Drdn1edge_security.c19 .dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
29 .acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
/trusted-firmware-a-latest/plat/arm/board/sgi575/
Dsgi575_security.c19 .dmc_count = ARRAY_SIZE(sgi575_dmc_base)
29 .acc_addr_count = ARRAY_SIZE(sgi575_acc_addr_data)
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/
Dsoc.c66 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in plat_get_power_domain_tree_desc()
102 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_tot_num_cores()
114 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_pmu_idle_cluster_mask()
126 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in get_pmu_flush_cluster_mask()
324 ARRAY_SIZE(ls_interrupt_props), in soc_platform_setup()
349 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); in soc_init()
354 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); in soc_init()
/trusted-firmware-a-latest/include/services/
Dsdei.h85 [PLATFORM_CORE_COUNT * ARRAY_SIZE(_private)]; \
86 sdei_entry_t sdei_shared_event_table[ARRAY_SIZE(_shared)]; \
90 .num_maps = ARRAY_SIZE(_private) \
94 .num_maps = ARRAY_SIZE(_shared) \
/trusted-firmware-a-latest/drivers/renesas/rzg/qos/G2N/
Dqos_init_g2n_v10.c100 rzg_qos_dbsc_setting(g2n_v10_qos, ARRAY_SIZE(g2n_v10_qos), true); in qos_init_g2n_v10()
150 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2n_v10()
154 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2n_v10()
159 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2n_v10()
163 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_g2n_v10()
/trusted-firmware-a-latest/drivers/renesas/rcar/qos/M3N/
Dqos_init_m3n_v10.c101 rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true); in qos_init_m3n_v10()
152 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3n_v10()
156 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3n_v10()
161 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3n_v10()
167 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) { in qos_init_m3n_v10()
/trusted-firmware-a-latest/plat/hisilicon/poplar/
Dpoplar_gicv2.c27 .interrupt_props_num = ARRAY_SIZE(poplar_interrupt_props),
29 .target_masks_num = ARRAY_SIZE(target_mask_array),
/trusted-firmware-a-latest/plat/st/stm32mp1/
Dstm32mp1_scmi.c68 assert(agent_id < ARRAY_SIZE(scmi_channel)); in plat_scmi_get_channel()
140 .clock_count = ARRAY_SIZE(stm32_scmi0_clock),
142 .rstd_count = ARRAY_SIZE(stm32_scmi0_reset_domain),
146 .clock_count = ARRAY_SIZE(stm32_scmi1_clock),
152 assert(agent_id < ARRAY_SIZE(agent_resources)); in find_resource()
163 for (n = 0U; n < ARRAY_SIZE(agent_resources); n++) { in plat_scmi_protocol_count_paranoid()
170 for (n = 0U; n < ARRAY_SIZE(agent_resources); n++) { in plat_scmi_protocol_count_paranoid()
203 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; in plat_scmi_protocol_count()
213 (ARRAY_SIZE(plat_protocol_list) - 1U)); in plat_scmi_protocol_list()
450 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) { in stm32mp1_init_scmi_server()
[all …]

12345678910