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Searched refs:enable (Results 1 – 25 of 119) sorted by relevance

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/trusted-firmware-a-3.7.0/plat/arm/common/
Darm_nor_psci_mem_protect.c53 unsigned long enable = (val != 0) ? 1UL : 0UL; in arm_nor_psci_write_mem_protect() local
60 if (enable == 1UL) { in arm_nor_psci_write_mem_protect()
74 if (nor_word_program(PLAT_ARM_MEM_PROT_ADDR, enable) != 0) { in arm_nor_psci_write_mem_protect()
97 int enable; in arm_nor_psci_do_dyn_mem_protect() local
99 arm_psci_read_mem_protect(&enable); in arm_nor_psci_do_dyn_mem_protect()
100 if (enable == 0) in arm_nor_psci_do_dyn_mem_protect()
117 int enable; in arm_nor_psci_do_static_mem_protect() local
119 (void) arm_psci_read_mem_protect(&enable); in arm_nor_psci_do_static_mem_protect()
120 if (enable == 0) in arm_nor_psci_do_static_mem_protect()
/trusted-firmware-a-3.7.0/plat/socionext/uniphier/
Duniphier_cci.c37 void (*enable)(void); member
44 .enable = NULL,
49 .enable = __uniphier_cci_enable,
54 .enable = NULL,
73 if (uniphier_cci_ops.enable) in uniphier_cci_enable()
74 uniphier_cci_ops.enable(); in uniphier_cci_enable()
/trusted-firmware-a-3.7.0/plat/arm/board/tc/fdts/
Dtc_spmc_manifest.dts63 enable-method = "psci";
74 enable-method = "psci";
81 enable-method = "psci";
88 enable-method = "psci";
95 enable-method = "psci";
102 enable-method = "psci";
109 enable-method = "psci";
116 enable-method = "psci";
Dtc_spmc_optee_sp_manifest.dts62 enable-method = "psci";
73 enable-method = "psci";
80 enable-method = "psci";
87 enable-method = "psci";
94 enable-method = "psci";
101 enable-method = "psci";
108 enable-method = "psci";
115 enable-method = "psci";
/trusted-firmware-a-3.7.0/plat/mediatek/mt8195/drivers/apusys/
Dapupwr_clkctl.h14 void apupwr_smc_acc_top(bool enable);
17 int32_t apupwr_smc_bulk_pll(bool enable);
20 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
Dapupll.c312 static void _pll_iso(uint32_t pll_idx, bool enable) in _pll_iso() argument
314 if (enable) { in _pll_iso()
379 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en) in apu_pll_enable() argument
389 if (enable) { in apu_pll_enable()
394 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
402 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
410 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
418 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
436 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
446 _pll_switch(pll_idx, enable, fhctl_en); in apu_pll_enable()
[all …]
Dapupwr_clkctl.c96 void apupwr_smc_acc_top(bool enable) in apupwr_smc_acc_top() argument
98 if (enable) { in apupwr_smc_acc_top()
313 int32_t apupwr_smc_bulk_pll(bool enable) in apupwr_smc_bulk_pll() argument
318 if (enable) { in apupwr_smc_bulk_pll()
320 ret = apu_pll_enable(pll_idx, enable, false); in apupwr_smc_bulk_pll()
327 ret = apu_pll_enable(pll_idx, enable, false); in apupwr_smc_bulk_pll()
/trusted-firmware-a-3.7.0/plat/hisilicon/hikey/
Dhisi_pwrc.c57 unsigned int val, enable; in hisi_pwrc_enable_debug() local
59 enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); in hisi_pwrc_enable_debug()
63 mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable); in hisi_pwrc_enable_debug()
67 } while (!(val & enable)); in hisi_pwrc_enable_debug()
/trusted-firmware-a-3.7.0/drivers/clk/
Dclk.c18 assert((ops != NULL) && (ops->enable != NULL)); in clk_enable()
20 return ops->enable(id); in clk_enable()
58 (ops_ptr->enable != NULL) && in clk_register()
/trusted-firmware-a-3.7.0/plat/arm/board/fvp/
Dfvp_sync_traps.c20 static void enable_rng_trap(bool enable) in enable_rng_trap() argument
24 if (enable) { in enable_rng_trap()
/trusted-firmware-a-3.7.0/plat/mediatek/mt8173/drivers/wdt/
Dwdt.c71 void wdt_set_enable(int enable) in wdt_set_enable() argument
73 if (enable) in wdt_set_enable()
76 WDT_MODE_KEY | (enable ? WDT_MODE_EN : 0)); in wdt_set_enable()
Dwdt.h14 void wdt_set_enable(int enable);
/trusted-firmware-a-3.7.0/lib/psci/
Dpsci_mem_protect.c14 u_register_t psci_mem_protect(unsigned int enable) in psci_mem_protect() argument
23 if (psci_plat_pm_ops->write_mem_protect(enable) < 0) in psci_mem_protect()
/trusted-firmware-a-3.7.0/plat/mediatek/drivers/gpio/
Dmtgpio_common.c91 static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable, in mt_gpio_set_spec_pull_pupd() argument
103 if (enable == MT_GPIO_PULL_ENABLE) { in mt_gpio_set_spec_pull_pupd()
116 static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable, in mt_gpio_set_pull_pu_pd() argument
129 if (enable == MT_GPIO_PULL_ENABLE) { in mt_gpio_set_pull_pu_pd()
143 static void mt_gpio_set_pull_chip(uint32_t pin, int enable, in mt_gpio_set_pull_chip() argument
150 mt_gpio_set_spec_pull_pupd(pin, enable, select); in mt_gpio_set_pull_chip()
152 mt_gpio_set_pull_pu_pd(pin, enable, select); in mt_gpio_set_pull_chip()
/trusted-firmware-a-3.7.0/fdts/
Dn1sdp-multi-chip.dts14 enable-method = "psci";
21 enable-method = "psci";
28 enable-method = "psci";
35 enable-method = "psci";
Dtc.dts89 enable-at-el3;
95 enable-at-el3;
101 enable-at-el3;
110 enable-method = "psci";
122 enable-method = "psci";
134 enable-method = "psci";
146 enable-method = "psci";
158 enable-method = "psci";
170 enable-method = "psci";
182 enable-method = "psci";
[all …]
Dmorello-fvp.dts80 enable-method = "psci";
88 enable-method = "psci";
96 enable-method = "psci";
104 enable-method = "psci";
Dn1sdp.dtsi21 enable-method = "psci";
28 enable-method = "psci";
35 enable-method = "psci";
42 enable-method = "psci";
/trusted-firmware-a-3.7.0/include/drivers/
Dclk.h13 int (*enable)(unsigned long id); member
/trusted-firmware-a-3.7.0/docs/components/fconf/
Damu-bindings.rst65 | ``enable-at-el3`` | O | ``<empty>`` | The presence of this property |
90 enable-at-el3;
96 enable-at-el3;
107 enable-at-el3;
/trusted-firmware-a-3.7.0/drivers/mtd/nand/
Dspi_nand.c83 static int spi_nand_ecc_enable(bool enable) in spi_nand_ecc_enable() argument
86 enable ? SPI_NAND_CFG_ECC_EN : 0U); in spi_nand_ecc_enable()
91 bool enable = false; in spi_nand_quad_enable() local
99 enable = true; in spi_nand_quad_enable()
103 enable ? SPI_NAND_CFG_QE : 0U); in spi_nand_quad_enable()
/trusted-firmware-a-3.7.0/docs/getting_started/
Dbuild-internals.rst16 - ``FFH_SUPPORT``: This boolean option provides support to enable Firmware First
21 which will enable this option implicitly.
Dbuild-options.rst61 - ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset
70 - ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
76 enable this use-case. For now, this option is only supported
108 - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
194 - ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
255 - ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
265 - ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
269 and this option can be used to enable this feature on those systems as well.
272 - ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
277 - ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
[all …]
/trusted-firmware-a-3.7.0/plat/imx/common/
Dimx_clock.c40 void imx_clock_gate_enable(unsigned int id, bool enable) in imx_clock_gate_enable() argument
49 if (enable) in imx_clock_gate_enable()
/trusted-firmware-a-3.7.0/include/lib/extensions/
Damu.h53 uint16_t enable; /* Mask of auxiliary counters to enable */ member

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