| /trusted-firmware-a-3.7.0/plat/mediatek/mt8183/drivers/mcdi/ |
| D | mtk_mcdi.c | 38 void sspm_standbywfi_irq_enable(uint32_t cpu_idx) in sspm_standbywfi_irq_enable() argument
40 mmio_write_32(SSPM_CFGREG_ACAO_INT_SET, STANDBYWFI_EN(cpu_idx)); in sspm_standbywfi_irq_enable()
88 static uint32_t target_mask(int cluster, int cpu_idx, bool on) in target_mask() argument
96 if (cpu_idx >= 0) in target_mask()
97 t |= BIT(cpu_idx + CPU_ON_OFS); in target_mask()
102 if (cpu_idx >= 0) in target_mask()
103 t |= BIT(cpu_idx + CPU_OFF_OFS); in target_mask()
109 void mcdi_pause_clr(int cluster, int cpu_idx, bool on) in mcdi_pause_clr() argument
111 uint32_t tgt = target_mask(cluster, cpu_idx, on); in mcdi_pause_clr()
118 void mcdi_pause_set(int cluster, int cpu_idx, bool on) in mcdi_pause_set() argument
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| D | mtk_mcdi.h | 13 void sspm_standbywfi_irq_enable(uint32_t cpu_idx);
25 void mcdi_pause_set(int cluster, int cpu_idx, bool on);
26 void mcdi_pause_clr(int cluster, int cpu_idx, bool on);
27 void mcdi_hotplug_set(int cluster, int cpu_idx, bool on);
28 void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on);
29 void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on);
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| /trusted-firmware-a-3.7.0/lib/psci/ |
| D | psci_common.c | 174 unsigned int cpu_start_idx, ncpus, cpu_idx; in psci_is_last_cpu_to_idle_at_pwrlvl() local
190 for (cpu_idx = cpu_start_idx; cpu_idx < cpu_start_idx + ncpus; in psci_is_last_cpu_to_idle_at_pwrlvl()
191 cpu_idx++) { in psci_is_last_cpu_to_idle_at_pwrlvl()
192 local_state = psci_get_cpu_local_state_by_idx(cpu_idx); in psci_is_last_cpu_to_idle_at_pwrlvl()
193 if (cpu_idx == my_idx) { in psci_is_last_cpu_to_idle_at_pwrlvl()
214 unsigned int cpu_idx, my_idx = plat_my_core_pos(); in psci_is_last_on_cpu() local
216 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { in psci_is_last_on_cpu()
217 if (cpu_idx == my_idx) { in psci_is_last_on_cpu()
222 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) { in psci_is_last_on_cpu()
224 cpu_idx, my_idx, "running in the system"); in psci_is_last_on_cpu()
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| D | psci_stat.c | 80 unsigned int cpu_idx = plat_my_core_pos(); in psci_stats_update_pwr_down() local
85 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; in psci_stats_update_pwr_down()
97 last_cpu_in_non_cpu_pd[parent_idx] = (int)cpu_idx; in psci_stats_update_pwr_down()
113 unsigned int cpu_idx = plat_my_core_pos(); in psci_stats_update_pwr_up() local
127 state_info, cpu_idx); in psci_stats_update_pwr_up()
130 psci_cpu_stat[cpu_idx][stat_idx].residency += residency; in psci_stats_update_pwr_up()
131 psci_cpu_stat[cpu_idx][stat_idx].count++; in psci_stats_update_pwr_up()
137 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; in psci_stats_update_pwr_up()
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| D | psci_on.c | 163 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) in psci_cpu_on_finish() argument
201 psci_spin_lock_cpu(cpu_idx); in psci_cpu_on_finish()
202 psci_spin_unlock_cpu(cpu_idx); in psci_cpu_on_finish()
219 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; in psci_cpu_on_finish()
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| D | psci_setup.c | 97 unsigned int cpu_idx; in psci_update_pwrlvl_limits() local
102 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { in psci_update_pwrlvl_limits()
103 psci_get_parent_pwr_domain_nodes(cpu_idx, in psci_update_pwrlvl_limits()
110 = cpu_idx; in psci_update_pwrlvl_limits()
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| D | psci_private.h | 292 unsigned int cpu_idx,
295 void psci_restore_req_local_pwr_states(unsigned int cpu_idx,
304 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
340 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
351 void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info);
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| D | psci_suspend.c | 28 static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, in psci_suspend_to_standby_finisher() argument
35 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); in psci_suspend_to_standby_finisher()
321 void psci_cpu_suspend_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) in psci_cpu_suspend_finish() argument
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| D | psci_main.c | 63 unsigned int cpu_idx = plat_my_core_pos(); in psci_cpu_suspend() local
108 psci_update_req_local_pwr_states(target_pwrlvl, cpu_idx, in psci_cpu_suspend()
134 psci_restore_req_local_pwr_states(cpu_idx, prev); in psci_cpu_suspend()
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| /trusted-firmware-a-3.7.0/bl31/ |
| D | bl31_context_mgmt.c | 45 void *cm_get_context_by_index(unsigned int cpu_idx, in cm_get_context_by_index() argument
50 return get_cpu_data_by_index(cpu_idx, in cm_get_context_by_index()
58 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
63 set_cpu_data_by_index(cpu_idx, in cm_set_context_by_index()
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| /trusted-firmware-a-3.7.0/include/lib/el3_runtime/ |
| D | context_mgmt.h | 25 void *cm_get_context_by_index(unsigned int cpu_idx,
27 void cm_set_context_by_index(unsigned int cpu_idx,
33 void cm_init_context_by_index(unsigned int cpu_idx,
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| /trusted-firmware-a-3.7.0/bl32/sp_min/ |
| D | sp_min_main.c | 91 void *cm_get_context_by_index(unsigned int cpu_idx, in cm_get_context_by_index() argument
95 return sp_min_cpu_ctx_ptr[cpu_idx]; in cm_get_context_by_index()
102 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
106 sp_min_cpu_ctx_ptr[cpu_idx] = context; in cm_set_context_by_index()
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| /trusted-firmware-a-3.7.0/plat/imx/imx8m/imx8mq/ |
| D | gpc.c | 183 static void imx_gpc_set_affinity(uint32_t hwirq, unsigned int cpu_idx) in imx_gpc_set_affinity() argument
188 if (hwirq >= MAX_HW_IRQ_NUM || cpu_idx >= 4) { in imx_gpc_set_affinity()
196 gpc_imr_core_spin_lock(cpu_idx); in imx_gpc_set_affinity()
197 reg = gpc_imr_offset[cpu_idx] + (hwirq / 32) * 4; in imx_gpc_set_affinity()
201 gpc_imr_core_spin_unlock(cpu_idx); in imx_gpc_set_affinity()
205 if (cpu_idx != i) { in imx_gpc_set_affinity()
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| /trusted-firmware-a-3.7.0/drivers/arm/css/scp/ |
| D | css_pm_scmi.c | 250 unsigned int channel_id, cpu_idx, domain_id; in css_scp_get_power_state() local
260 cpu_idx = (unsigned int)plat_core_pos_by_mpidr(mpidr); in css_scp_get_power_state()
261 assert(cpu_idx < PLATFORM_CORE_COUNT); in css_scp_get_power_state()
263 css_scp_core_pos_to_scmi_channel(cpu_idx, &domain_id, &channel_id); in css_scp_get_power_state()
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| /trusted-firmware-a-3.7.0/lib/el3_runtime/aarch32/ |
| D | context_mgmt.c | 163 void cm_init_context_by_index(unsigned int cpu_idx, in cm_init_context_by_index() argument
167 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); in cm_init_context_by_index()
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| /trusted-firmware-a-3.7.0/docs/getting_started/ |
| D | psci-lib-integration-guide.rst | 354 Argument : unsigned int cpu_idx, void *context, unsigned int security_state
362 by ``cpu_idx`` (first argument). The ``security_state`` will always be non-secure
364 with BL31. The ``cpu_idx`` will correspond to the index returned by the
389 Argument : unsigned int cpu_idx, unsigned int security_state
394 ``cpu_idx`` (first argument). The caller must ensure that
398 retained for compatibility with BL31. The ``cpu_idx`` will correspond to the
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| /trusted-firmware-a-3.7.0/lib/el3_runtime/aarch64/ |
| D | context_mgmt.c | 793 void cm_init_context_by_index(unsigned int cpu_idx, in cm_init_context_by_index() argument
797 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); in cm_init_context_by_index()
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| /trusted-firmware-a-3.7.0/docs/ |
| D | change-log.md | 6554 - Unify type of "cpu_idx" and Platform specific defines across PSCI module.
6855 - Unify type of "cpu_idx" across PSCI module.
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