| /trusted-firmware-a-3.7.0/plat/xilinx/common/include/ |
| D | pm_api_sys.h | 74 #define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \ argument
75 pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \
78 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ argument
80 PM_PACK_PAYLOAD1(pl, (mid), (flag), (arg0)); \
83 #define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ argument
85 PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \
88 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
90 PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
93 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
95 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
[all …]
|
| /trusted-firmware-a-3.7.0/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| D | mce.c | 158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler() argument
177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
190 ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, in mce_command_handler()
201 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); in mce_command_handler()
206 ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); in mce_command_handler()
215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler()
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
237 ret = ops->online_core(cpu_ari_base, arg0); in mce_command_handler()
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
[all …]
|
| /trusted-firmware-a-3.7.0/plat/xilinx/zynqmp/pm_service/ |
| D | zynqmp_pm_api_sys.h | 41 #define PM_PACK_PAYLOAD1(pl, arg0) { \ argument
42 pl[0] = (uint32_t)(arg0); \
45 #define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \ argument
47 PM_PACK_PAYLOAD1(pl, arg0); \
50 #define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \ argument
52 PM_PACK_PAYLOAD2(pl, arg0, arg1); \
55 #define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \ argument
57 PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \
60 #define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \
[all …]
|
| /trusted-firmware-a-3.7.0/plat/rockchip/rk3399/ |
| D | plat_sip_calls.c | 30 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, in ddr_smc_handler() argument
35 return ddr_set_rate((uint32_t)arg0); in ddr_smc_handler()
37 return ddr_round_rate((uint32_t)arg0); in ddr_smc_handler()
41 dram_set_odt_pd(arg0, arg1, arg2); in ddr_smc_handler()
|
| /trusted-firmware-a-3.7.0/bl2/ |
| D | bl2_main.c | 41 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_el3_setup() argument
45 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_el3_setup()
63 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_setup() argument
67 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_setup()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/fvp_ve/sp_min/ |
| D | fvp_ve_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/corstone700/sp_min/ |
| D | corstone700_sp_min_setup.c | 9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/a5ds/sp_min/ |
| D | a5ds_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
|
| /trusted-firmware-a-3.7.0/plat/arm/common/sp_min/ |
| D | arm_sp_min_setup.c | 96 bl33_image_ep_info.args.arg0 = 0U; in arm_sp_min_early_platform_setup()
136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/a5ds/ |
| D | a5ds_bl2_setup.c | 9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/include/bl2/ |
| D | bl2.h | 12 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
14 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
|
| /trusted-firmware-a-3.7.0/plat/arm/board/fvp_ve/ |
| D | fvp_ve_bl2_setup.c | 16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/bl32/tsp/ |
| D | tsp_private.h | 51 smc_args_t *set_smc_args(uint64_t arg0,
67 smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
76 smc_args_t *tsp_cpu_off_main(uint64_t arg0,
124 smc_args_t *tsp_system_reset_main(uint64_t arg0,
133 smc_args_t *tsp_system_off_main(uint64_t arg0,
|
| D | tsp_common.c | 34 smc_args_t *set_smc_args(uint64_t arg0, in set_smc_args() argument
52 write_sp_arg(pcpu_smc_args, SMC_ARG0, arg0); in set_smc_args()
88 smc_args_t *tsp_system_off_main(uint64_t arg0, in tsp_system_off_main() argument
116 smc_args_t *tsp_system_reset_main(uint64_t arg0, in tsp_system_reset_main() argument
|
| /trusted-firmware-a-3.7.0/plat/mediatek/drivers/dfd/ |
| D | dfd.c | 13 static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, in dfd_smc_dispatcher() argument
19 switch (arg0) { in dfd_smc_dispatcher()
|
| /trusted-firmware-a-3.7.0/plat/rpi/rpi3/ |
| D | rpi3_bl31_setup.c | 70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
84 bl_params_t *params_from_bl2 = (bl_params_t *) arg0; in bl31_early_platform_setup2()
122 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
133 bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/plat/qemu/common/ |
| D | qemu_bl2_setup.c | 58 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
298 bl_mem_params->ep_info.args.arg0 = in qemu_bl2_handle_post_image_load()
324 bl_mem_params->ep_info.args.arg0 = in qemu_bl2_handle_post_image_load()
352 bl_mem_params->ep_info.args.arg0 = 0; in qemu_bl2_handle_post_image_load()
358 bl_mem_params->ep_info.args.arg0 = te ? in qemu_bl2_handle_post_image_load()
365 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in qemu_bl2_handle_post_image_load()
369 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in qemu_bl2_handle_post_image_load()
382 bl32_mem_params->ep_info.args.arg0 = in qemu_bl2_handle_post_image_load()
|
| /trusted-firmware-a-3.7.0/plat/brcm/common/ |
| D | brcm_bl31_setup.c | 133 bl33_image_ep_info.args.arg0 = (u_register_t)PRELOADED_DTB_BASE; in brcm_bl31_early_platform_setup()
181 bl33_image_ep_info.args.arg0 = (u_register_t)BL33_SHARED_DDR_BASE; in brcm_bl31_early_platform_setup()
188 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
195 brcm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
197 plat_bcm_bl31_early_platform_setup((void *)arg0, (void *)arg3); in bl31_early_platform_setup2()
|
| D | brcm_bl2_setup.c | 64 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
158 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); in bcm_bl2_handle_post_image_load()
|
| /trusted-firmware-a-3.7.0/plat/nuvoton/npcm845x/ |
| D | npcm845x_bl31_setup.c | 117 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
121 void *from_bl2 = (void *)arg0; in bl31_early_platform_setup2()
162 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in bl31_early_platform_setup2()
190 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; in bl31_early_platform_setup2()
200 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/plat/arm/board/juno/ |
| D | juno_bl31_setup.c | 15 void __init bl31_early_platform_setup2(u_register_t arg0, in bl31_early_platform_setup2() argument
30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/plat/arm/css/common/ |
| D | css_bl2_setup.c | 56 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
|
| /trusted-firmware-a-3.7.0/lib/optee/ |
| D | optee_utils.c | 146 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
148 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
200 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
203 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
|
| /trusted-firmware-a-3.7.0/plat/rockchip/common/ |
| D | sp_min_plat_setup.c | 52 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
66 bl31_params_parse_helper(arg0, NULL, &bl33_ep_info); in sp_min_early_platform_setup2()
|
| D | bl31_plat_setup.c | 57 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
71 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); in bl31_early_platform_setup2()
|
