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Searched refs:SSC_REG_BASE (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-a-3.7.0/plat/arm/board/juno/
Djuno_security.c122 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET, in init_debug_cfg()
126 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR, in init_debug_cfg()
130 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET, in init_debug_cfg()
134 mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR, in init_debug_cfg()
/trusted-firmware-a-3.7.0/include/plat/arm/css/common/
Dcss_def.h25 #define SSC_REG_BASE 0x2a420000 macro
26 #define SSC_GPRETN (SSC_REG_BASE + 0x030)
/trusted-firmware-a-3.7.0/plat/arm/css/sgi/include/
Dsgi_base_platform_def.h245 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
/trusted-firmware-a-3.7.0/plat/arm/board/morello/include/
Dplatform_def.h247 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
/trusted-firmware-a-3.7.0/plat/arm/board/n1sdp/include/
Dplatform_def.h278 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)