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Searched refs:SCTLR (Results 1 – 23 of 23) sorted by relevance

/trusted-firmware-a-3.7.0/lib/psci/aarch32/
Dpsci_helpers.S89 ldcopr r0, SCTLR
91 stcopr r0, SCTLR
109 ldcopr r1, SCTLR
111 stcopr r1, SCTLR
/trusted-firmware-a-3.7.0/lib/cpus/aarch32/
Daem_generic.S15 ldcopr r0, SCTLR
31 ldcopr r0, SCTLR
Dcortex_a32.S56 ldcopr r0, SCTLR
87 ldcopr r0, SCTLR
Dcortex_a12.S15 ldcopr r0, SCTLR
Dcortex_a5.S15 ldcopr r0, SCTLR
Dcortex_a7.S15 ldcopr r0, SCTLR
Dcortex_a72.S159 ldcopr r0, SCTLR
206 ldcopr r0, SCTLR
Dcortex_a53.S237 ldcopr r0, SCTLR
267 ldcopr r0, SCTLR
Dcortex_a9.S15 ldcopr r0, SCTLR
Dcortex_a15.S21 ldcopr r0, SCTLR
Dcortex_a17.S15 ldcopr r0, SCTLR
Dcortex_a57.S522 ldcopr r0, SCTLR
564 ldcopr r0, SCTLR
/trusted-firmware-a-3.7.0/lib/xlat_tables_v2/aarch32/
Denable_mmu.S18 ldcopr r1, SCTLR
56 ldcopr r1, SCTLR
64 stcopr r1, SCTLR
/trusted-firmware-a-3.7.0/bl2u/aarch32/
Dbl2u_entrypoint.S48 ldcopr r0, SCTLR
51 stcopr r0, SCTLR
/trusted-firmware-a-3.7.0/bl2/aarch32/
Dbl2_entrypoint.S49 ldcopr r0, SCTLR
52 stcopr r0, SCTLR
/trusted-firmware-a-3.7.0/bl1/aarch32/
Dbl1_exceptions.S130 ldcopr r9, SCTLR
132 stcopr r9, SCTLR
/trusted-firmware-a-3.7.0/include/arch/aarch32/
Del3_common_macros.S34 ldcopr r0, SCTLR
36 stcopr r0, SCTLR
272 stcopr r0, SCTLR
Darch_helpers.h233 DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR) in DEFINE_SYSREG_RW_FUNCS()
Darch.h531 #define SCTLR p15, 0, c1, c0, 0 macro
/trusted-firmware-a-3.7.0/lib/aarch32/
Dmisc_helpers.S182 ldcopr r0, SCTLR
184 stcopr r0, SCTLR
/trusted-firmware-a-3.7.0/docs/getting_started/
Dpsci-lib-integration-guide.rst102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
/trusted-firmware-a-3.7.0/docs/design/
Dfirmware-design.rst715 SCTLR.EE = 0
777 SCTLR.EE = 0
/trusted-firmware-a-3.7.0/docs/
Dchange-log.md6843 - AArch64: Fix SCTLR bit definitions
6854 - SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
7752 SCTLR is explicitly initialised during the warmboot flow rather than relying