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/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3399/include/shared/
Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
77 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
86 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) argument
87 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) argument
88 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) argument
[all …]
Daddressmap_shared.h91 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) argument
92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) argument
95 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) argument
96 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) argument
99 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) argument
100 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) argument
102 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) argument
/trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
28 ((n) << (8 + (ch) * 4)))
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
30 ((n) << (9 + (ch) * 4)))
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) in phy_pctrl_reset() argument
138 rkclk_ddr_reset(ch, 1, 1); in phy_pctrl_reset()
140 rkclk_ddr_reset(ch, 1, 0); in phy_pctrl_reset()
142 rkclk_ddr_reset(ch, 0, 0); in phy_pctrl_reset()
146 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) in set_cs_training_index() argument
152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
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Ddram.c26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init() local
27 struct rk3399_msch_timings *noc = &ch->noc_timings; in dram_init()
32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); in dram_init()
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); in dram_init()
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); in dram_init()
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); in dram_init()
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); in dram_init()
38 ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); in dram_init()
39 ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); in dram_init()
[all …]
Ddfs.c84 struct rk3399_sdram_channel *ch = &ram_config->ch[channel]; in get_cs_die_capability() local
91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; in get_cs_die_capability()
92 bandwidth = 8 * (1 << ch->bw); in get_cs_die_capability()
93 die_bandwidth = 8 * (1 << ch->dbw); in get_cs_die_capability()
95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + in get_cs_die_capability()
97 if (ch->row_3_4) in get_cs_die_capability()
188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()
189 for (j = 0; j < sdram_params->ch[i].rank; j++) { in sdram_timing_cfg_init()
1412 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, in gen_rk3399_phy_dll_bypass() argument
1432 mmio_setbits_32(PHY_REG(ch, 514), 1); in gen_rk3399_phy_dll_bypass()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/css/scmi/
Dscmi_common.c29 void scmi_get_channel(scmi_channel_t *ch) in scmi_get_channel() argument
31 assert(ch->lock); in scmi_get_channel()
32 scmi_lock_get(ch->lock); in scmi_get_channel()
36 ((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); in scmi_get_channel()
42 void scmi_send_sync_command(scmi_channel_t *ch) in scmi_send_sync_command() argument
44 mailbox_mem_t *mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_send_sync_command()
55 ch->info->ring_doorbell(ch->info); in scmi_send_sync_command()
77 void scmi_put_channel(scmi_channel_t *ch) in scmi_put_channel() argument
81 ((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); in scmi_put_channel()
83 assert(ch->lock); in scmi_put_channel()
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Dscmi_sys_pwr_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_set() local
25 validate_scmi_channel(ch); in scmi_sys_pwr_state_set()
27 scmi_get_channel(ch); in scmi_sys_pwr_state_set()
29 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_sys_pwr_state_set()
36 scmi_send_sync_command(ch); in scmi_sys_pwr_state_set()
43 scmi_put_channel(ch); in scmi_sys_pwr_state_set()
56 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_get() local
58 validate_scmi_channel(ch); in scmi_sys_pwr_state_get()
60 scmi_get_channel(ch); in scmi_sys_pwr_state_get()
62 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_sys_pwr_state_get()
[all …]
Dscmi_ap_core_proto.c23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_set_reset_addr() local
25 validate_scmi_channel(ch); in scmi_ap_core_set_reset_addr()
27 scmi_get_channel(ch); in scmi_ap_core_set_reset_addr()
29 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_ap_core_set_reset_addr()
37 scmi_send_sync_command(ch); in scmi_ap_core_set_reset_addr()
44 scmi_put_channel(ch); in scmi_ap_core_set_reset_addr()
57 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_get_reset_addr() local
60 validate_scmi_channel(ch); in scmi_ap_core_get_reset_addr()
62 scmi_get_channel(ch); in scmi_ap_core_get_reset_addr()
64 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_ap_core_get_reset_addr()
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Dscmi_pwr_dmn_proto.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_set() local
32 validate_scmi_channel(ch); in scmi_pwr_state_set()
34 scmi_get_channel(ch); in scmi_pwr_state_set()
36 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_pwr_state_set()
44 scmi_send_sync_command(ch); in scmi_pwr_state_set()
51 scmi_put_channel(ch); in scmi_pwr_state_set()
65 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_get() local
67 validate_scmi_channel(ch); in scmi_pwr_state_get()
69 scmi_get_channel(ch); in scmi_pwr_state_get()
71 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_pwr_state_get()
[all …]
Dscmi_private.h145 void scmi_get_channel(scmi_channel_t *ch);
146 void scmi_send_sync_command(scmi_channel_t *ch);
147 void scmi_put_channel(scmi_channel_t *ch);
149 static inline void validate_scmi_channel(scmi_channel_t *ch) in validate_scmi_channel() argument
151 assert(ch && ch->is_initialized); in validate_scmi_channel()
152 assert(ch->info && ch->info->scmi_mbx_mem); in validate_scmi_channel()
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/drivers/bpmp/
Dbpmp.c24 static uint32_t channel_field(unsigned int ch) in channel_field() argument
26 return mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET) & CH_MASK(ch); in channel_field()
29 static bool master_free(unsigned int ch) in master_free() argument
31 return channel_field(ch) == MA_FREE(ch); in master_free()
34 static bool master_acked(unsigned int ch) in master_acked() argument
36 return channel_field(ch) == MA_ACKD(ch); in master_acked()
39 static void signal_slave(unsigned int ch) in signal_slave() argument
41 mmio_write_32(TEGRA_RES_SEMA_BASE + CLR_OFFSET, CH_MASK(ch)); in signal_slave()
44 static void free_master(unsigned int ch) in free_master() argument
47 MA_ACKD(ch) ^ MA_FREE(ch)); in free_master()
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/trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/ddr/ddr_b/
Dboot_init_dram.c246 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
248 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
249 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
253 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
268 static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
318 static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
319 static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
326 static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
327 static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
342 #define foreach_vch(ch) \ argument
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Dboot_init_dram_regdef.h31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
64 #define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) argument
/trusted-firmware-a-3.6.0-3.5.0/drivers/renesas/common/
Dddr_regs.h16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
96 #define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) argument
101 #define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) argument
106 #define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) argument
111 #define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) argument
116 #define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) argument
121 #define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) argument
126 #define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) argument
131 #define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) argument
132 #define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) argument
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/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/css/scmi/vendor/
Dscmi_sq.c30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_get_draminfo() local
33 validate_scmi_channel(ch); in scmi_get_draminfo()
35 scmi_get_channel(ch); in scmi_get_draminfo()
37 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_get_draminfo()
43 scmi_send_sync_command(ch); in scmi_get_draminfo()
57 scmi_put_channel(ch); in scmi_get_draminfo()
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/include/drivers/
Dbpmp.h22 #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
23 #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) argument
24 #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
/trusted-firmware-a-3.6.0-3.5.0/lib/libc/
Dstrchr.c41 strchr(const char *p, int ch) in strchr() argument
45 c = ch; in strchr()
Dstrrchr.c36 strrchr(const char *p, int ch) in strrchr() argument
41 c = ch; in strrchr()
Dprintf.c178 char ch = *fmt; in vprintf() local
179 if ((ch < '0') || (ch > '9')) { in vprintf()
182 padn = (padn * 10) + (ch - '0'); in vprintf()
/trusted-firmware-a-3.6.0-3.5.0/services/spd/trusty/
Dgeneric-arm64-smcall.c40 static void trusty_dputc(char ch, int secure) in trusty_dputc() argument
48 s->linebuf[s->l++] = ch; in trusty_dputc()
49 if (s->l == sizeof(s->linebuf) || ch == '\n') { in trusty_dputc()
57 if (ch != '\n') { in trusty_dputc()
/trusted-firmware-a-3.6.0-3.5.0/drivers/arm/dcc/
Ddcc_console.c92 static int32_t dcc_console_putc(int32_t ch, struct console *console) in dcc_console_putc() argument
100 __dcc_putchar(ch); in dcc_console_putc()
102 return ch; in dcc_console_putc()
/trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/drivers/bpmp_ipc/
Divc.c75 volatile const struct ivc_channel_header *ch) in ivc_channel_empty() argument
82 uint32_t wr_count = ch->w_count; in ivc_channel_empty()
83 uint32_t rd_count = ch->r_count; in ivc_channel_empty()
106 volatile const struct ivc_channel_header *ch) in ivc_channel_full() argument
108 uint32_t wr_count = ch->w_count; in ivc_channel_full()
109 uint32_t rd_count = ch->r_count; in ivc_channel_full()
121 volatile const struct ivc_channel_header *ch) in ivc_channel_avail_count() argument
123 uint32_t wr_count = ch->w_count; in ivc_channel_avail_count()
124 uint32_t rd_count = ch->r_count; in ivc_channel_avail_count()
222 volatile const struct ivc_channel_header *ch, in ivc_frame_pointer() argument
[all …]
/trusted-firmware-a-3.6.0-3.5.0/plat/socionext/synquacer/drivers/scp/
Dsq_scmi.c202 static int scmi_ap_core_init(scmi_channel_t *ch) in scmi_ap_core_init() argument
208 ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); in scmi_ap_core_init()
/trusted-firmware-a-3.6.0-3.5.0/include/lib/libc/
Dstring.h27 char *strrchr(const char *p, int ch);
/trusted-firmware-a-3.6.0-3.5.0/drivers/marvell/mochi/
Dapn806_setup.c70 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000) argument

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