Lines Matching refs:ch
27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
28 ((n) << (8 + (ch) * 4)))
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
30 ((n) << (9 + (ch) * 4)))
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) in phy_pctrl_reset() argument
138 rkclk_ddr_reset(ch, 1, 1); in phy_pctrl_reset()
140 rkclk_ddr_reset(ch, 1, 0); in phy_pctrl_reset()
142 rkclk_ddr_reset(ch, 0, 0); in phy_pctrl_reset()
146 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) in set_cs_training_index() argument
152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
156 static __pmusramfunc void select_per_cs_training_index(uint32_t ch, in select_per_cs_training_index() argument
160 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) in select_per_cs_training_index()
161 set_cs_training_index(ch, rank); in select_per_cs_training_index()
164 static __pmusramfunc void override_write_leveling_value(uint32_t ch) in override_write_leveling_value() argument
173 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
175 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
184 static __pmusramfunc int data_training(uint32_t ch, in data_training() argument
189 uint32_t rank = sdram_params->ch[ch].rank; in data_training()
199 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
223 select_per_cs_training_index(ch, i); in data_training()
225 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); in data_training()
228 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
233 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
239 obs_0 = mmio_read_32(PHY_REG(ch, 532)); in data_training()
240 obs_1 = mmio_read_32(PHY_REG(ch, 660)); in data_training()
241 obs_2 = mmio_read_32(PHY_REG(ch, 788)); in data_training()
256 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); in data_training()
258 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training()
264 select_per_cs_training_index(ch, i); in data_training()
266 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); in data_training()
268 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
274 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
281 obs_0 = mmio_read_32(PHY_REG(ch, 40)); in data_training()
282 obs_1 = mmio_read_32(PHY_REG(ch, 168)); in data_training()
283 obs_2 = mmio_read_32(PHY_REG(ch, 296)); in data_training()
284 obs_3 = mmio_read_32(PHY_REG(ch, 424)); in data_training()
301 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); in data_training()
303 override_write_leveling_value(ch); in data_training()
304 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training()
310 select_per_cs_training_index(ch, i); in data_training()
312 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
318 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
324 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
331 obs_0 = mmio_read_32(PHY_REG(ch, 43)); in data_training()
332 obs_1 = mmio_read_32(PHY_REG(ch, 171)); in data_training()
333 obs_2 = mmio_read_32(PHY_REG(ch, 299)); in data_training()
334 obs_3 = mmio_read_32(PHY_REG(ch, 427)); in data_training()
350 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); in data_training()
352 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training()
358 select_per_cs_training_index(ch, i); in data_training()
360 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, in data_training()
363 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
368 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
383 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); in data_training()
385 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training()
394 select_per_cs_training_index(ch, i); in data_training()
399 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training()
401 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, in data_training()
404 mmio_clrsetbits_32(PI_REG(ch, 121), in data_training()
409 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
418 mmio_write_32(PI_REG(ch, 175), 0x00003f7c); in data_training()
420 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training()
424 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
434 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; in set_ddrconfig() local
438 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20)); in set_ddrconfig()
439 if (ch->rank > 1) in set_ddrconfig()
440 cs1_cap = cs0_cap >> (ch->cs0_row - ch->cs1_row); in set_ddrconfig()
441 if (ch->row_3_4) { in set_ddrconfig()
458 struct rk3399_sdram_channel *info = &sdram_params->ch[i]; in dram_all_config()
461 if (sdram_params->ch[i].col == 0) in dram_all_config()
475 if (sdram_params->ch[i].rank == 1) in dram_all_config()
489 static __pmusramfunc void pctl_cfg(uint32_t ch, in pctl_cfg() argument
501 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1], in pctl_cfg()
503 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); in pctl_cfg()
504 sram_regcpy(PI_REG(ch, 0), (uintptr_t)¶ms_pi[0], in pctl_cfg()
507 sram_regcpy(PHY_REG(ch, 910), (uintptr_t)&phy_regs->phy896[910 - 896], in pctl_cfg()
510 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, in pctl_cfg()
514 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24); in pctl_cfg()
517 mmio_setbits_32(PI_REG(ch, 0), START); in pctl_cfg()
518 mmio_setbits_32(CTL_REG(ch, 0), START); in pctl_cfg()
522 tmp = mmio_read_32(PHY_REG(ch, 920)); in pctl_cfg()
523 tmp1 = mmio_read_32(PHY_REG(ch, 921)); in pctl_cfg()
524 tmp2 = mmio_read_32(PHY_REG(ch, 922)); in pctl_cfg()
531 if (mmio_read_32(PHY_REG(ch, 911)) & 0x1) in pctl_cfg()
535 sram_regcpy(PHY_REG(ch, 896), (uintptr_t)&phy_regs->phy896[0], 63); in pctl_cfg()
538 sram_regcpy(PHY_REG(ch, 128 * i), in pctl_cfg()
542 sram_regcpy(PHY_REG(ch, 512 + 128 * i), in pctl_cfg()
549 uint32_t ch, ch_count; in dram_switch_to_next_index() local
565 for (ch = 0; ch < ch_count; ch++) { in dram_switch_to_next_index()
571 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, in dram_switch_to_next_index()
576 if (data_training(ch, sdram_params, PI_FULL_TRAINING)) in dram_switch_to_next_index()
701 uint32_t ch, byte, i; in dmc_suspend() local
745 for (ch = 0; ch < sdram_params->num_channels; ch++) { in dmc_suspend()
747 sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) & in dmc_suspend()
748 mmio_read_32(PHY_REG(ch, 57 + byte * 128)); in dmc_suspend()
758 __pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq) in phy_dll_bypass_set() argument
762 mmio_setbits_32(PHY_REG(ch, 86), 3 << 10); in phy_dll_bypass_set()
763 mmio_setbits_32(PHY_REG(ch, 214), 3 << 10); in phy_dll_bypass_set()
764 mmio_setbits_32(PHY_REG(ch, 342), 3 << 10); in phy_dll_bypass_set()
765 mmio_setbits_32(PHY_REG(ch, 470), 3 << 10); in phy_dll_bypass_set()
767 mmio_setbits_32(PHY_REG(ch, 547), 3 << 18); in phy_dll_bypass_set()
768 mmio_setbits_32(PHY_REG(ch, 675), 3 << 18); in phy_dll_bypass_set()
769 mmio_setbits_32(PHY_REG(ch, 803), 3 << 18); in phy_dll_bypass_set()
772 mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10); in phy_dll_bypass_set()
773 mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10); in phy_dll_bypass_set()
774 mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10); in phy_dll_bypass_set()
775 mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10); in phy_dll_bypass_set()
777 mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18); in phy_dll_bypass_set()
778 mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18); in phy_dll_bypass_set()
779 mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18); in phy_dll_bypass_set()
824 if (sdram_params->ch[channel].col) in dmc_resume()
845 sdram_params->ch[channel].ddrconfig); in dmc_resume()