| /trusted-firmware-a-3.6.0-3.5.0/lib/psci/ |
| D | psci_common.c | 45 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
75 CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
266 pwrlvl = PLAT_MAX_PWR_LVL; in get_power_on_target_pwrlvl()
281 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()
296 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { in psci_init_req_local_pwr_states()
317 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_get_req_local_pwr_states()
339 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; in psci_update_req_local_pwr_states()
368 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; in psci_restore_req_local_pwr_states()
444 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_get_target_local_pwr_states()
[all …]
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| D | psci_setup.c | 99 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; in psci_update_pwrlvl_limits()
100 unsigned int temp_index[PLAT_MAX_PWR_LVL]; in psci_update_pwrlvl_limits()
104 PLAT_MAX_PWR_LVL, in psci_update_pwrlvl_limits()
106 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { in psci_update_pwrlvl_limits()
129 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree()
230 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); in psci_setup()
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| D | psci_off.c | 27 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
49 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_do_cpu_off()
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| D | psci_main.c | 65 plat_local_state_t prev[PLAT_MAX_PWR_LVL]; in psci_cpu_suspend()
202 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) in psci_system_suspend()
209 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); in psci_system_suspend()
217 PLAT_MAX_PWR_LVL, in psci_system_suspend()
227 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; in psci_cpu_off()
347 if (power_level > PLAT_MAX_PWR_LVL) in psci_node_hw_state()
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| D | psci_suspend.c | 31 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_suspend_to_standby_finisher()
82 end_pwrlvl = PLAT_MAX_PWR_LVL; in psci_suspend_to_pwrdown_start()
170 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_cpu_suspend_start()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/imx/common/ |
| D | imx8_psci.c | 39 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/css/common/ |
| D | css_pm.c | 42 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
55 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
62 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
279 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); in css_get_sys_suspend_power_state()
281 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) in css_get_sys_suspend_power_state()
310 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) in css_validate_power_state()
376 psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); in css_reboot_interrupt_handler()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/common/ |
| D | arm_pm.c | 33 if (pwr_lvl > PLAT_MAX_PWR_LVL) in arm_validate_power_state()
99 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { in arm_validate_power_state()
149 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_save()
178 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_resume()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/rockchip/common/ |
| D | plat_pm.c | 26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
141 if (pwr_lvl > PLAT_MAX_PWR_LVL) in rockchip_validate_power_state()
160 for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++) in rockchip_validate_power_state()
176 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
231 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
267 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
288 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
332 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/intel/soc/common/ |
| D | socfpga_psci.c | 68 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_off()
84 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend()
100 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_on_finish()
123 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend_finish()
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| /trusted-firmware-a-3.6.0-3.5.0/services/spd/tlkd/ |
| D | tlkd_pm.c | 50 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_suspend_handler()
83 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_resume_handler()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/mt8173/ |
| D | plat_pm.c | 39 #define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
59 #if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
378 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
387 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
436 assert(PLAT_MAX_PWR_LVL >= 2); in plat_get_sys_suspend_power_state()
438 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in plat_get_sys_suspend_power_state()
478 if (pwr_lvl > PLAT_MAX_PWR_LVL) in plat_validate_power_state()
548 assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2); in mtk_system_pwr_domain_resume()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/zynqmp/ |
| D | plat_psci.c | 67 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_off()
92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in zynqmp_pwr_domain_suspend()
111 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_on_finish()
124 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_suspend_finish()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/versal_net/ |
| D | plat_psci_pm.c | 62 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_off()
109 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend()
152 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in versal_net_pwr_domain_suspend_finish()
226 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in versal_net_get_sys_suspend_power_state()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/imx/imx8m/imx8mq/ |
| D | imx8mq_psci.c | 28 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
125 for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
128 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/nvidia/tegra/common/ |
| D | tegra_pm.c | 40 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in tegra_get_sys_suspend_power_state()
148 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_power_down_wfi()
171 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_on_finish()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/xilinx/versal/ |
| D | plat_psci.c | 57 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_suspend()
94 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_suspend_finish()
162 for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { in versal_pwr_domain_off()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/allwinner/common/ |
| D | sunxi_scpi_pm.c | 138 if (power_level > PLAT_MAX_PWR_LVL) { in sunxi_validate_power_state()
155 for (; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_validate_power_state()
166 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_get_sys_suspend_power_state()
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| D | sunxi_topology.c | 12 static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
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| /trusted-firmware-a-3.6.0-3.5.0/plat/mediatek/include/armv8_2/ |
| D | arch_def.h | 11 #define PLAT_MAX_PWR_LVL (2) macro
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| /trusted-firmware-a-3.6.0-3.5.0/plat/qti/msm8916/ |
| D | msm8916_topology.c | 12 static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
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| /trusted-firmware-a-3.6.0-3.5.0/drivers/arm/css/scp/ |
| D | css_pm_scmi.c | 143 for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_suspend()
189 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in css_scp_off()
222 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in css_scp_on()
253 if ((power_level > PLAT_MAX_PWR_LVL) || in css_scp_get_power_state()
342 psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); in css_scp_system_off()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/renesas/common/ |
| D | plat_pm.c | 35 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
283 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
289 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
290 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
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| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/board/rde1edge/include/ |
| D | platform_def.h | 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 macro
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| /trusted-firmware-a-3.6.0-3.5.0/plat/arm/board/sgi575/include/ |
| D | platform_def.h | 28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 macro
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