| /trusted-firmware-a-3.4.0/drivers/rpi3/gpio/ |
| D | rpi3_gpio.c | 49 uint32_t sel = mmio_read_32(reg_sel); in rpi3_gpio_get_select() local
51 ret = (sel >> shift) & 0x07; in rpi3_gpio_get_select()
74 uint32_t sel = mmio_read_32(reg_sel); in rpi3_gpio_set_select() local
77 sel = (sel & (~mask)) | ((fsel << shift) & mask); in rpi3_gpio_set_select()
78 mmio_write_32(reg_sel, sel); in rpi3_gpio_set_select()
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| /trusted-firmware-a-3.4.0/drivers/st/clk/ |
| D | clk-stm32-core.c | 287 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) in clk_mux_set_parent() argument
297 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); in clk_mux_set_parent()
320 uint8_t sel; in _clk_stm32_set_parent() local
339 for (sel = 0; sel < parents->num_parents; sel++) { in _clk_stm32_set_parent()
340 if (parents->id_parents[sel] == (uint16_t)clkp) { in _clk_stm32_set_parent()
348 err = clk_mux_set_parent(priv, pid, sel); in _clk_stm32_set_parent()
383 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel) in _clk_stm32_set_parent_by_index() argument
393 return clk_mux_set_parent(priv, pid, sel); in _clk_stm32_set_parent_by_index()
401 int sel; in _clk_stm32_get_parent() local
416 sel = clk->ops->get_parent(priv, clk_id); in _clk_stm32_get_parent()
[all …]
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| D | stm32mp1_clk.c | 244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ member
276 .sel = (s), \
288 .sel = _UNKNOWN_SEL, \
300 .sel = (s), \
312 .sel = _UNKNOWN_SEL, \
732 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); in stm32mp1_clk_get_sel()
742 const struct stm32mp1_clk_sel *sel; in stm32mp1_clk_get_parent() local
773 sel = clk_sel_ref(s); in stm32mp1_clk_get_parent()
774 p_sel = (mmio_read_32(rcc_base + sel->offset) & in stm32mp1_clk_get_parent()
775 (sel->msk << sel->src)) >> sel->src; in stm32mp1_clk_get_parent()
[all …]
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| D | clk-stm32-core.h | 174 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel);
214 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel);
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| D | clk-stm32mp13.c | 1107 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; in stm32_clk_configure_clk() local
1117 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); in stm32_clk_configure_clk()
1134 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
1136 return clk_mux_set_parent(priv, mux, sel); in stm32_clk_configure_mux()
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| /trusted-firmware-a-3.4.0/plat/mediatek/common/drivers/gpio/ |
| D | mtgpio_common.c | 220 static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel) in mt_set_gpio_pull_select_chip() argument
224 if (sel == MT_GPIO_PULL_NONE) { in mt_set_gpio_pull_select_chip()
226 } else if (sel == MT_GPIO_PULL_UP) { in mt_set_gpio_pull_select_chip()
228 } else if (sel == MT_GPIO_PULL_DOWN) { in mt_set_gpio_pull_select_chip()
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| /trusted-firmware-a-3.4.0/include/dt-bindings/clock/ |
| D | stm32mp13-clksrc.h | 72 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
74 (sel)))
77 #define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
79 (sel)) | CLK_ON_MASK)
85 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
87 (sel)) | CLK_ON_MASK)
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| /trusted-firmware-a-3.4.0/plat/mediatek/mt8183/drivers/gpio/ |
| D | mtgpio.c | 287 void mt_set_gpio_pull_select_chip(uint32_t pin, int sel) in mt_set_gpio_pull_select_chip() argument
298 if (sel == GPIO_PULL_NONE) { in mt_set_gpio_pull_select_chip()
306 } else if (sel == GPIO_PULL_UP) { in mt_set_gpio_pull_select_chip()
313 } else if (sel == GPIO_PULL_DOWN) { in mt_set_gpio_pull_select_chip()
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| /trusted-firmware-a-3.4.0/drivers/ufs/ |
| D | ufs.c | 395 uint8_t index, uint8_t sel, in ufs_prepare_query() argument
420 query_upiu->ts.desc.selector = sel; in ufs_prepare_query()
592 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, in ufs_query() argument
612 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); in ufs_query()
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