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Searched refs:reg_base (Results 1 – 25 of 30) sorted by relevance

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/trusted-firmware-a-3.4.0/drivers/rpi3/sdhost/
Drpi3_sdhost.c50 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_waitcommand() local
54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in send_command_raw() local
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
81 mmio_write_32(reg_base + HC_HOSTSTATUS, status); in send_command_raw()
87 mmio_write_32(reg_base + HC_ARGUMENT, arg); in send_command_raw()
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE); in send_command_raw()
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_drain_fifo() local
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
[all …]
/trusted-firmware-a-3.4.0/drivers/imx/usdhc/
Dimx_usdhc.c44 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
58 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
59 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
62 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
68 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
70 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); in imx_usdhc_initialize()
73 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); in imx_usdhc_initialize()
76 while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) { in imx_usdhc_initialize()
82 mmio_write_32(reg_base + MMCBOOT, 0); in imx_usdhc_initialize()
83 mmio_write_32(reg_base + MIXCTRL, 0); in imx_usdhc_initialize()
[all …]
Dimx_usdhc.h13 uintptr_t reg_base; member
/trusted-firmware-a-3.4.0/drivers/rpi3/gpio/
Drpi3_gpio.c14 static uintptr_t reg_base; variable
48 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_get_select()
73 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_set_select()
109 uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN); in rpi3_gpio_get_value()
121 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
122 uintptr_t reg_clr = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
138 uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD; in rpi3_gpio_set_pull()
139 uintptr_t reg_clk = reg_base + RPI3_GPIO_GPPUDCLK(regN); in rpi3_gpio_set_pull()
161 reg_base = RPI3_GPIO_BASE; in rpi3_gpio_init()
/trusted-firmware-a-3.4.0/plat/socionext/uniphier/
Duniphier_nand.c52 uintptr_t reg_base; member
88 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0); in uniphier_nand_block_isbad()
90 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_block_isbad()
103 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_block_isbad()
125 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1); in uniphier_nand_read_pages()
126 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1); in uniphier_nand_read_pages()
128 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_read_pages()
148 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_read_pages()
151 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0); in uniphier_nand_read_pages()
241 nand->reg_base = nand->host_base + 0x100000; in uniphier_nand_hw_init()
[all …]
/trusted-firmware-a-3.4.0/drivers/synopsys/emmc/
Ddw_mmc.c145 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
152 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); in dw_update_clk()
173 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); in dw_set_clk()
177 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
184 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
185 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
194 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); in dw_init()
196 base = dw_params.reg_base; in dw_init()
[all …]
/trusted-firmware-a-3.4.0/drivers/ufs/
Dufs.c63 assert(ufs_params.reg_base != 0); in ufshc_dme_get()
68 base = ufs_params.reg_base; in ufshc_dme_get()
104 assert((ufs_params.reg_base != 0)); in ufshc_dme_set()
106 base = ufs_params.reg_base; in ufshc_dme_set()
243 data = mmio_read_32(ufs_params.reg_base + UTRLDBR); in get_empty_slot()
303 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_cmd()
305 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_cmd()
405 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_query()
407 mmio_write_32(ufs_params.reg_base + UTRLBAU, in ufs_prepare_query()
457 mmio_write_32(ufs_params.reg_base + UTRLBA, in ufs_prepare_nop_out()
[all …]
/trusted-firmware-a-3.4.0/drivers/marvell/comphy/
Dphy-comphy-3700.c614 uintptr_t reg_base = 0; in mvebu_a3700_comphy_usb3_power_on() local
632 reg_base = COMPHY_INDIRECT_REG; in mvebu_a3700_comphy_usb3_power_on()
636 reg_base = USB3_GBE1_PHY; in mvebu_a3700_comphy_usb3_power_on()
649 usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask); in mvebu_a3700_comphy_usb3_power_on()
661 usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
666 usb3_reg_set(reg_base, COMPHY_LANE_CFG4, in mvebu_a3700_comphy_usb3_power_on()
673 usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL, in mvebu_a3700_comphy_usb3_power_on()
680 usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0, in mvebu_a3700_comphy_usb3_power_on()
688 usb3_reg_set(reg_base, COMPHY_GEN2_SET2, in mvebu_a3700_comphy_usb3_power_on()
697 usb3_reg_set(reg_base, COMPHY_GEN3_SET2, in mvebu_a3700_comphy_usb3_power_on()
[all …]
/trusted-firmware-a-3.4.0/drivers/synopsys/ufs/
Ddw_ufs.c23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
/trusted-firmware-a-3.4.0/drivers/imx/timer/
Dimx_gpt.h12 void imx_gpt_ops_init(uintptr_t reg_base);
/trusted-firmware-a-3.4.0/include/drivers/synopsys/
Ddw_mmc.h13 uintptr_t reg_base; member
/trusted-firmware-a-3.4.0/include/drivers/st/
Dstm32_sdmmc2.h16 uintptr_t reg_base; member
/trusted-firmware-a-3.4.0/plat/intel/soc/common/include/
Dsocfpga_private.h20 .reg_base = SOCFPGA_MMC_REG_BASE \
/trusted-firmware-a-3.4.0/plat/st/common/
Dbl2_io_storage.c205 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
208 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
211 params.reg_base = STM32MP_SDMMC3_BASE; in boot_mmc()
216 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
218 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
Dbl2_stm32_io_storage.c354 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
357 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
360 params.reg_base = STM32MP_SDMMC3_BASE; in boot_mmc()
365 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
367 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
/trusted-firmware-a-3.4.0/include/drivers/
Ddw_ufs.h102 uintptr_t reg_base; member
/trusted-firmware-a-3.4.0/drivers/st/mmc/
Dstm32_sdmmc2.c161 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_init()
223 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_send_cmd_req()
454 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_set_ios()
508 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_prepare()
574 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_read()
678 sdmmc2_params.reg_base); in stm32_sdmmc2_dt_get_config()
743 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && in stm32_sdmmc2_mmc_init()
/trusted-firmware-a-3.4.0/plat/hisilicon/poplar/include/
Dhi3798cv200.h75 .reg_base = REG_BASE_MCI, \
/trusted-firmware-a-3.4.0/plat/imx/imx8m/imx8mm/
Dimx8mm_bl2_el3_setup.c46 params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE; in imx8mm_usdhc_setup()
/trusted-firmware-a-3.4.0/include/drivers/rpi3/sdhost/
Drpi3_sdhost.h16 uintptr_t reg_base; member
/trusted-firmware-a-3.4.0/plat/rpi/rpi3/
Drpi3_bl2_setup.c35 params.reg_base = RPI3_SDHOST_BASE; in rpi3_sdhost_setup()
/trusted-firmware-a-3.4.0/plat/imx/imx7/warp7/
Dwarp7_bl2_el3_setup.c106 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; in warp7_usdhc_setup()
/trusted-firmware-a-3.4.0/plat/hisilicon/hikey/
Dhikey_bl1_setup.c98 params.reg_base = DWMMC0_BASE; in bl1_platform_setup()
/trusted-firmware-a-3.4.0/plat/imx/imx7/picopi/
Dpicopi_bl2_el3_setup.c100 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; in picopi_usdhc_setup()
/trusted-firmware-a-3.4.0/drivers/st/spi/
Dstm32_qspi.c109 uintptr_t reg_base; member
120 return stm32_qspi.reg_base; in qspi_base()
470 &stm32_qspi.reg_base, &size); in stm32_qspi_init()

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