| /trusted-firmware-a-3.4.0/plat/common/ |
| D | plat_bl1_common.c | 83 meminfo_t *bl2_secram_layout; in bl1_plat_handle_post_image_load()
84 meminfo_t *bl1_secram_layout; in bl1_plat_handle_post_image_load()
108 bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; in bl1_plat_handle_post_image_load()
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| /trusted-firmware-a-3.4.0/plat/qemu/common/ |
| D | qemu_bl1_setup.c | 18 static meminfo_t bl1_tzram_layout;
21 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
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| D | qemu_bl2_setup.c | 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
32 meminfo_t *mem_layout = (void *)arg1; in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/plat/arm/board/fvp_r/ |
| D | fvp_r_bl1_setup.c | 52 static meminfo_t bl1_tzram_layout;
214 meminfo_t *bl33_secram_layout; in bl1_plat_handle_post_image_load()
215 meminfo_t *bl1_secram_layout; in bl1_plat_handle_post_image_load()
239 bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; in bl1_plat_handle_post_image_load()
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| D | fvp_r_bl1_main.c | 98 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, in bl1_calc_bl2_mem_layout()
99 meminfo_t *bl2_mem_layout) in bl1_calc_bl2_mem_layout()
112 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); in bl1_calc_bl2_mem_layout()
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| /trusted-firmware-a-3.4.0/plat/hisilicon/poplar/ |
| D | bl1_plat_setup.c | 29 static meminfo_t bl1_tzram_layout;
30 static meminfo_t bl2_tzram_layout;
59 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); in bl1_plat_handle_post_image_load()
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| D | bl2_plat_setup.c | 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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| /trusted-firmware-a-3.4.0/plat/rpi/rpi3/ |
| D | rpi3_bl2_setup.c | 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
51 meminfo_t *mem_layout = (meminfo_t *) arg1; in bl2_early_platform_setup2()
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| D | rpi3_bl1_setup.c | 20 static meminfo_t bl1_tzram_layout;
22 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
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| /trusted-firmware-a-3.4.0/plat/marvell/armada/common/ |
| D | marvell_bl1_setup.c | 26 static meminfo_t bl1_ram_layout;
28 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
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| D | marvell_bl2_setup.c | 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
35 meminfo_t *bl2_plat_sec_mem_layout(void) in bl2_plat_sec_mem_layout()
46 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) in marvell_bl2_early_platform_setup()
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| /trusted-firmware-a-3.4.0/plat/brcm/common/ |
| D | brcm_bl2_setup.c | 22 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
48 meminfo_t *mem_layout) in bcm_bl2_early_platform_setup()
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/include/bl1/ |
| D | bl1.h | 98 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
99 meminfo_t *bl2_mem_layout);
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| /trusted-firmware-a-3.4.0/plat/arm/board/a5ds/ |
| D | a5ds_bl2_setup.c | 12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/bl1/ |
| D | bl1_main.c | 38 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, in bl1_calc_bl2_mem_layout()
39 meminfo_t *bl2_mem_layout) in bl1_calc_bl2_mem_layout()
52 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); in bl1_calc_bl2_mem_layout()
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| /trusted-firmware-a-3.4.0/plat/arm/board/fvp_ve/ |
| D | fvp_ve_bl2_setup.c | 18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/plat/hisilicon/hikey/ |
| D | hikey_bl1_setup.c | 30 static meminfo_t bl1_tzram_layout;
40 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
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| /trusted-firmware-a-3.4.0/plat/arm/css/common/ |
| D | css_bl2u_setup.c | 25 void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) in bl2u_early_platform_setup()
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| D | css_bl2_setup.c | 59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/plat/arm/common/ |
| D | arm_bl2_el3_setup.c | 23 static meminfo_t bl2_el3_tzram_layout;
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| D | arm_bl2_setup.c | 35 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
94 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /trusted-firmware-a-3.4.0/include/plat/marvell/armada/a3k/common/ |
| D | plat_marvell.h | 64 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
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| /trusted-firmware-a-3.4.0/plat/hisilicon/hikey960/ |
| D | hikey960_bl1_setup.c | 43 static meminfo_t bl1_tzram_layout;
64 meminfo_t *bl1_plat_sec_mem_layout(void) in bl1_plat_sec_mem_layout()
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| /trusted-firmware-a-3.4.0/include/plat/marvell/armada/a8k/common/ |
| D | plat_marvell.h | 79 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout);
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| /trusted-firmware-a-3.4.0/plat/arm/board/fvp/ |
| D | fvp_bl2_setup.c | 23 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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