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Searched refs:SRAM_STREAM_BASE (Results 1 – 14 of 14) sorted by relevance

/sof-2.7.6/src/platform/imx8/include/platform/lib/
Dmemory.h95 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
99 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
Dmailbox.h53 #define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
/sof-2.7.6/src/platform/amd/renoir/include/platform/lib/
Dmemory.h72 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
76 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
Dmailbox.h38 #define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
/sof-2.7.6/src/platform/imx8m/include/platform/lib/
Dmemory.h98 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
102 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
Dmailbox.h53 #define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
/sof-2.7.6/src/platform/imx8ulp/include/platform/lib/
Dmemory.h98 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
102 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
Dmailbox.h53 #define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
/sof-2.7.6/src/platform/suecreek/include/platform/lib/
Dmemory.h206 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
209 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
/sof-2.7.6/src/platform/intel/cavs/include/cavs/lib/
Dmailbox.h56 #define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
/sof-2.7.6/src/platform/icelake/include/platform/lib/
Dmemory.h199 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
203 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
/sof-2.7.6/src/platform/cannonlake/include/platform/lib/
Dmemory.h202 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
206 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
/sof-2.7.6/src/platform/apollolake/include/platform/lib/
Dmemory.h197 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
201 #define SRAM_INBOX_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
/sof-2.7.6/src/platform/tigerlake/include/platform/lib/
Dmemory.h202 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) macro
206 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)