Home
last modified time | relevance | path

Searched refs:SHIM_CLKCTL_LMCS_DIV4 (Results 1 – 9 of 9) sorted by relevance

/sof-2.7.6/src/platform/tigerlake/lib/
Dclk.c20 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
22 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
24 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
/sof-2.7.6/src/platform/suecreek/lib/
Dclk.c19 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
21 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
/sof-2.7.6/src/platform/icelake/lib/
Dclk.c19 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
21 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
/sof-2.7.6/src/platform/cannonlake/lib/
Dclk.c19 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
21 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
/sof-2.7.6/src/platform/suecreek/include/platform/lib/
Dshim.h130 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro
163 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
/sof-2.7.6/src/platform/icelake/include/platform/lib/
Dshim.h138 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro
168 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
/sof-2.7.6/src/platform/cannonlake/include/platform/lib/
Dshim.h144 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro
174 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
/sof-2.7.6/src/platform/tigerlake/include/platform/lib/
Dshim.h142 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro
172 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
/sof-2.7.6/src/platform/intel/cavs/
Dplatform.c444 SHIM_CLKCTL_LMCS_DIV4 | /* LP mem clock div by 4 */ in platform_init()