Searched refs:SHIM_CLKCTL_LMCS_DIV4 (Results 1 – 9 of 9) sorted by relevance
20 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,22 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,24 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
19 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,21 SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
130 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro163 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
138 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro168 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
144 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro174 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
142 #define SHIM_CLKCTL_LMCS_DIV4 BIT(1) macro172 (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
444 SHIM_CLKCTL_LMCS_DIV4 | /* LP mem clock div by 4 */ in platform_init()